公开(公告)号：US11836893B2

公开(公告)日：2023-12-05

申请号：US17167356

申请日：2021-02-04

Applicant: MediaTek Inc.

Inventor： Cheng Lung Jen ,  Pei-Kuei Tsung ,  Yao-Sheng Wang ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Ming-En Shih ,  Kuo-Chiang Lo

IPC: G06T3/40 ,  G06N3/04 ,  H04L65/75 ,  G06F18/214 ,  G06V10/764 ,  G06V10/774 ,  G06V20/40

CPC classification number: G06T3/4053 ,  G06F18/214 ,  G06N3/04 ,  G06T3/4046 ,  G06T3/4076 ,  G06V10/764 ,  G06V10/774 ,  G06V20/41 ,  H04L65/75

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.

公开(公告)号：US20210287339A1

公开(公告)日：2021-09-16

申请号：US17196957

申请日：2021-03-09

Applicant: MEDIATEK INC.

Inventor： Ming-En Shih ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Pei-Kuei Tsung ,  Hsin-Min Peng ,  Ping-Yuan Tsai ,  Kuo-Chiang Lo ,  Chun-Hsien Wu ,  Chih-Wei Chen ,  Cheng-Lung Jen

IPC: G06T3/40 ,  G06T5/00

Abstract: An image processing apparatus includes a super-resolution (SR) circuit and a resizer circuit. The SR circuit performs an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, and the SR operation is based, at least in part, on one or more artificial intelligence (AI) models. The resizer circuit performs a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and no AI model is involved in the resize operation.

公开(公告)号：US20250077180A1

公开(公告)日：2025-03-06

申请号：US18820312

申请日：2024-08-30

Applicant: MEDIATEK INC.

Inventor： Ming-Hung Lin ,  Ming-En Shih ,  Shih-Wei Hsieh ,  Ping-Yuan Tsai ,  You-Yu Nian ,  Pei-Kuei Tsung ,  Jen-Wei Liang ,  Shu-Hsin Chang ,  En-Jui Chang ,  Chih-Wei Chen ,  Po-Hua Huang ,  Chung-Lun Huang

IPC: G06F7/505 ,  G06F7/57

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

公开(公告)号：US20250077282A1

公开(公告)日：2025-03-06

申请号：US18820342

申请日：2024-08-30

Applicant: MEDIATEK INC.

Inventor： Ming-Hung Lin ,  Ming-En Shih ,  Shih-Wei Hsieh ,  Ping-Yuan Tsai ,  You-Yu Nian ,  Pei-Kuei Tsung ,  Jen-Wei Liang ,  Shu-Hsin Chang ,  En-Jui Chang ,  Chih-Wei Chen ,  Po-Hua Huang ,  Chung-Lun Huang

IPC: G06F9/50 ,  G06F17/15

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

公开(公告)号：US20210287338A1

公开(公告)日：2021-09-16

申请号：US17118162

申请日：2020-12-10

Applicant: MediaTek Inc.

Inventor： Ming-En Shih ,  Ping-Yuan Tsai ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Kuo-Chiang Lo ,  Hsin-Min Peng ,  Chun Hsien Wu ,  Pei-Kuei Tsung ,  Tung-Chien Chen ,  Yao-Sheng Wang ,  Cheng Lung Jen ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Sheng Lin ,  Tsu Jui Hsu

IPC: G06T3/40 ,  G06T7/00 ,  G06T5/00 ,  G06N3/04 ,  G06N3/08

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligent (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

公开(公告)号：US12062151B2

公开(公告)日：2024-08-13

申请号：US17118162

申请日：2020-12-10

Applicant: MediaTek Inc.

Inventor： Ming-En Shih ,  Ping-Yuan Tsai ,  Yu-Cheng Tseng ,  Kuo-Chen Huang ,  Kuo-Chiang Lo ,  Hsin-Min Peng ,  Chun Hsien Wu ,  Pei-Kuei Tsung ,  Tung-Chien Chen ,  Yao-Sheng Wang ,  Cheng Lung Jen ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Sheng Lin ,  Tsu Jui Hsu

IPC: G06T3/4053 ,  G06F13/00 ,  G06N3/04 ,  G06N3/08 ,  G06T3/4046 ,  G06T5/70 ,  G06T7/00 ,  G09G5/391 ,  H01L21/033 ,  H04N9/31

CPC classification number: G06T3/4053 ,  G06F13/00 ,  G06N3/04 ,  G06N3/08 ,  G06T3/4046 ,  G06T5/70 ,  G06T7/0002 ,  G09G5/391 ,  H01L21/0338 ,  H04N9/3188 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30168

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

公开(公告)号：US20210287340A1

公开(公告)日：2021-09-16

申请号：US17167356

申请日：2021-02-04

Applicant: MediaTek Inc.

Inventor： Cheng Lung Jen ,  Pei-Kuei Tsung ,  Yao-Sheng Wang ,  Chih-Wei Chen ,  Chih-Wen Goo ,  Yu-Cheng Tseng ,  Ming-En Shih ,  Kuo-Chiang Lo

IPC: G06T3/40 ,  G06N3/04 ,  G06K9/62 ,  H04L29/06

Abstract: A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.