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Patent Agency Ranking
1.发明申请公开(公告)号：US20160291068A1
公开(公告)日：2016-10-06
申请号：US14933542
申请日：2015-11-05
Applicant: MEDIATEK INC.
Inventor： Huajun Wen , Hugh Thomas Mair , Hsin-Chen Chen , Brian King Flachs
CPC classification number: G06F1/3203 , G06F1/04
Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
Abstract translation: 动态功率计电路接收一组时钟信号。 时钟信号由时钟和加法器相加，从而产生时钟和值。 至少部分地基于时钟和值产生动态功率计输出值。 在一个具体示例中，动态功率计电路接收时钟信号，并从中产生时钟和模型子值。 动态功率计电路还接收事件信号，并从它们生成建筑事件模型子值。 然后将对应的一对时钟和模型子值和架构事件模型子值进行比例组合，从而生成动态功率计输出值。 由于使用了事件信号和时钟信号两者，所以产生动态功率计输出值流，其更紧密地跟踪被监控电路的实际动态功率。
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2.发明公开公开(公告)号：US20240146316A1
公开(公告)日：2024-05-02
申请号：US18490728
申请日：2023-10-19
Applicant: MediaTek Inc.
Inventor： Yu-Shu Chen , Hsin-Chen Chen , Kuan Hung Lin , Jeng-Yi Lin
CPC classification number: H03L7/0991 , G06F1/324 , H03L7/0995 , H03L2207/50
Abstract: A system performs a method of adaptive voltage scaling. The method includes generating a voltage adjustment signal based on a hint from a frequency-locked loop (FLL). The FLL includes an oscillator that generates a clock signal at a clock frequency. The voltage adjustment signal is sent to a power management unit (PMU) to cause the PMU to supply an adjusted operating voltage to the FLL. The method further includes updating a minimum code set according to the adjusted operating voltage and an operating temperature. The clock frequency of the oscillator is generated to match a target frequency according to the adjusted operating voltage and a code determined by the FLL from the minimum code set.
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公开(公告)号：US10345882B2
公开(公告)日：2019-07-09
申请号：US14933542
申请日：2015-11-05
Applicant: MEDIATEK INC.
Inventor： Huajun Wen , Hugh Thomas Mair , Hsin-Chen Chen , Brian King Flachs
IPC: G06F1/3203 , G06F1/04
Abstract: A dynamic power meter circuit receives a set of clock signals. The clock signals are summed by a clock sum adder, thereby generating a clock sum value. A dynamic power meter output value is generated based at least in part on the clock sum value. In one particular example, a dynamic power meter circuit receives clock signals and from them generates a clock sum model sub-value. The dynamic power meter circuit also receives event signals, and from them generates an architectural event model sub-value. A corresponding pair of clock sum model sub-value and architectural event model sub-value are then ratiometrically combined, thereby generating a dynamic power meter output value. Due to the use of both event signals and clock signals, a stream of dynamic power meter output values is generated that more closely tracks actual dynamic power of a circuit being monitored.
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公开(公告)号：US20140136177A1
公开(公告)日：2014-05-15
申请号：US13672723
申请日：2012-11-09
Applicant: MEDIATEK INC.
Inventor： Ming-Hsien Lee , Shih-Tsung Hsiao , Hsin-Chen Chen
IPC: G06F17/50
CPC classification number: G06F17/5054 , G06F2217/78
Abstract: A critical path emulating apparatus includes a critical path emulator (CPE) and an interconnection circuit. The CPE is capable of emulating a critical path of a target device, and supporting a plurality of speed information detection modes. The interconnection circuit is capable of supporting a plurality of interconnection arrangements, wherein when the interconnection circuit is configured to have a first interconnection arrangement, the CPE is capable of being used in a first speed information detection mode, and when the interconnection circuit is configured to have a second interconnection arrangement, the CPE is capable of being used in a second speed information detection mode.
Abstract translation: 关键路径仿真装置包括关键路径仿真器（CPE）和互连电路。 CPE能够模拟目标设备的关键路径，并支持多种速度信息检测模式。 互连电路能够支持多个互连布置，其中当互连电路被配置为具有第一互连布置时，CPE能够用于第一速度信息检测模式，并且当互连电路被配置为 具有第二互连布置，CPE能够用于第二速度信息检测模式。
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5.发明申请公开(公告)号：US20250093896A1
公开(公告)日：2025-03-20
申请号：US18885866
申请日：2024-09-16
Applicant: MediaTek Inc.
Inventor： Anshul Varma , Hsin-Chen Chen
Abstract: A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.
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