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    Chemical planarization performance for copper/low-k interconnect structures
    1.
    发明授权
    Chemical planarization performance for copper/low-k interconnect structures 有权
    铜/低k互连结构的化学平面化性能

    公开(公告)号：US07407879B2

    公开(公告)日：2008-08-05

    申请号：US11369476

    申请日：2006-03-07

    申请人： Lee M Nicholson ,  Wei-Tsu Tseng ,  Christy S Tyberg

    发明人： Lee M Nicholson ,  Wei-Tsu Tseng ,  Christy S Tyberg

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5329 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/7688 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

    摘要： An electrical interconnect structure on a substrate, which includes: a first low-k dielectric layer; a spin-on low k CMP protective layer that is covalently bonded to the first low-k dielectric layer; and a CVD deposited hardmask/CMP polish stop layer is provided. Electrical vias and lines can be formed in the first low k dielectric layer. The spin-on low k CMP protective layer prevents damage to the low k dielectric which can be created due to non-uniformity in the CMP process from center to edge or in areas of varying metal density. The thickness of the low-k CMP protective layer can be adjusted to accommodate larger variations in the CMP process without significantly impacting the effective dielectric constant of the structure.

    摘要翻译： 在基板上的电互连结构，其包括：第一低k电介质层; 共价键合到第一低k电介质层的自旋低k CMP保护层; 并提供CVD沉积的硬掩模/ CMP抛光停止层。 可以在第一低k电介质层中形成电通孔和线。 旋转低k CMP保护层可防止由于中心到边缘或不同金属密度区域的CMP工艺中的不均匀性而导致的低k电介质的损坏。 可以调节低k CMP保护层的厚度以适应CMP工艺中的较大变化，而不显着影响结构的有效介电常数。

    Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
    3.
    发明授权
    Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures 有权
    多孔低k电介质互连结构的韧性，粘附性和光滑的金属线

    公开(公告)号：US06783862B2

    公开(公告)日：2004-08-31

    申请号：US10290682

    申请日：2002-11-08

    申请人： Jeffrey C Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S Tyberg

    发明人： Jeffrey C Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S Tyberg

    IPC分类号： B32B904

    CPC分类号： H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

    摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

    摘要翻译： 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

    Dual damascene integration of ultra low dielectric constant porous materials
    4.
    发明授权
    Dual damascene integration of ultra low dielectric constant porous materials 失效
    双镶嵌一体化超低介电常数多孔材料

    公开(公告)号：US07737561B2

    公开(公告)日：2010-06-15

    申请号：US11968929

    申请日：2008-01-03

    申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

    发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

    摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔线路电平低k电介质层，其上具有金属线导体，其具有底部和侧壁; 在第一多孔线路低k电介质上的抛光停止层; 第二薄的无孔通孔级低k电介质层，用于涂覆和平坦化线和通孔侧壁; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

    Method for dual damascene integration of ultra low dielectric constant porous materials
    6.
    发明授权
    Method for dual damascene integration of ultra low dielectric constant porous materials 有权
    双金属镶嵌超低介电常数多孔材料的方法

    公开(公告)号：US07338895B2

    公开(公告)日：2008-03-04

    申请号：US11341338

    申请日：2006-01-26

    申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

    发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

    IPC分类号： H01L21/4763

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

    摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔低k线电介质层，其上具有底部和侧壁的金属线导体; 在第一多孔低k电介质上的抛光停止层; 用于涂覆和平坦化线和通孔侧壁的第二薄无孔低k介电层; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

    Dual damascene integration of ultra low dielectric constant porous materials
    7.
    发明授权
    Dual damascene integration of ultra low dielectric constant porous materials 失效
    双镶嵌一体化超低介电常数多孔材料

    公开(公告)号：US07057287B2

    公开(公告)日：2006-06-06

    申请号：US10645308

    申请日：2003-08-21

    申请人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

    发明人： Kaushik A Kumar ,  Kelly Malone ,  Christy S Tyberg

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

    摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔低k线电介质层，其上具有底部和侧壁的金属线导体; 在第一多孔低k电介质上的抛光停止层; 用于涂覆和平坦化线和通孔侧壁的第二薄无孔低k介电层; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。