公开(公告)号：US20140253226A1

公开(公告)日：2014-09-11

申请号：US13800120

申请日：2013-03-13

Applicant: LSI CORPORATION

Inventor： Ting Zhou ,  Ruggero Castagnetti ,  Chris Sonnek

IPC: G05F1/10

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  Y02D10/171

Abstract: An apparatus having one or more of a plurality of circuits in a first level of a hierarchy and two or more of the circuits in a second level of the hierarchy is disclosed. The circuits are configured to (i) allocate a profile from the first level down to the second level, (ii) manage from the second level a respective power consumed by each of a plurality of blocks based on the profile and (iii) maintain a sum of the powers approximately constant by increasing the power consumed by a first of the blocks while decreasing the power consumed by a second of the blocks.

Abstract translation: 公开了一种具有层次结构的第一级中的多个电路中的一个或多个并且在层次结构的第二级中的两个或更多个电路的装置。 电路被配置为（i）从第一级别分配到第二级别的简档，（ii）基于该简档从第二级别管理由多个块中的每一个消耗的相应功率，以及（iii）维护一个 通过在减少第二块的功率消耗的同时增加第一个块消耗的功率，功率的总和近似恒定。

公开(公告)号：US08724423B1

公开(公告)日：2014-05-13

申请号：US13712782

申请日：2012-12-12

Applicant: LSI Corporation

Inventor： Ting Zhou ,  Sheng Liu

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  G06F12/00 ,  G06F13/00 ,  G11C11/412 ,  G11C11/413 ,  G06F9/38 ,  G06F11/20

CPC classification number: G11C8/12 ,  G11C7/1075

Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.

Abstract translation: 可操作以提供并发双端口读取和双端口写入访问功能的存储器包括存储器阵列，其包括组织成多行存储体的第一和第二多个单端口存储器单元，以及多个校验和模块。 第二组多个存储单元作为备用存储体来操作。 校验和模块中的每一个都与相应的一行存储体相关联。 存储器还包括第一控制器和多个映射表。 第一控制器和第一和第二多个存储器单元的至少一部分使得存储器阵列能够支持双端口读或单端口写操作。 第二控制器用于接收读取和写入访问请求，并且经由映射表将逻辑和备用存储体标识符映射到对应的物理存储器组标识符，从而模拟并发的双端口读取和双端口写入访问功能。

公开(公告)号：US08923089B2

公开(公告)日：2014-12-30

申请号：US13725028

申请日：2012-12-21

Applicant: LSI Corporation

Inventor： Sheng Liu ,  Ting Zhou

IPC: G11C11/406 ,  G11C8/16 ,  G11C11/00

CPC classification number: G11C8/16

Abstract: A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The controller is operatively coupled to the first and second memory arrays, and resolves the memory access conflict by determining locations to store data in the first and second single-port memory cells to thereby avoid a collision between concurrent memory accesses to the first single-port memory cell in response to the memory access conflict. The controller determines locations to store data in the first and second single-port memory cells based on the location information.

Abstract translation: 存储设备提供单端口读取多端口写入功能，并且包括第一和第二存储器阵列和控制器。 第一存储器阵列包括第一和第二单端口存储器单元。 响应于与第一单端口存储器单元相关联的存储器访问冲突，第二单端口存储器单元存储数据。 第二存储器阵列存储与存储在第一和第二单端口存储器单元中的数据相关联的位置信息。 控制器可操作地耦合到第一和第二存储器阵列，并且通过确定在第一和第二单端口存储器单元中存储数据的位置来解决存储器访问冲突，从而避免在对第一单端口的并行存储器访问之间的冲突 内存单元响应内存访问冲突。 控制器基于位置信息确定在第一和第二单端口存储器单元中存储数据的位置。

公开(公告)号：US20140169113A1

公开(公告)日：2014-06-19

申请号：US13910582

申请日：2013-06-05

Applicant: LSI Corporation

Inventor： Ting Zhou ,  Ross A. Kohler ,  Ruggero Castagnetti ,  Michael G. Yee ,  Concetta Riccobene

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/82 ,  G11C29/814

Abstract: A memory system and a memory repair method for the memory system are disclosed. The method includes the steps of: organizing at least one repair block to serve as a shared repair resource for the plurality of memory blocks in the tiled memory; identifying a defective memory unit among the plurality of memory blocks in the tiled memory; identifying a replacement unit in the repair block for replacement of the defective memory unit; retrieving a set of memory blocks from the plurality of memory blocks in the tiled memory in response to a data access request, wherein the set of memory blocks retrieved containing the defective memory unit; retrieving the replacement unit from the repair block in response to the data access request; and replacing the defective memory unit in the set of memory blocks with the replacement unit.

Abstract translation: 公开了一种用于存储器系统的存储器系统和存储器修复方法。 该方法包括以下步骤：组织至少一个修复块以用作平铺存储器中的多个存储器块的共享修复资源; 识别所述平铺存储器中的所述多个存储器块中的有缺陷的存储器单元; 识别所述修理块中的替换单元以更换所述有缺陷的存储器单元; 响应于数据访问请求从所述平铺存储器中的所述多个存储器块中检索一组存储器块，其中所述包含所述有缺陷的存储器单元的所述存储器块集合; 响应于数据访问请求从修复块检索替换单元; 并用更换单元替换该组存储器块中的有缺陷的存储器单元。

公开(公告)号：US20140281284A1

公开(公告)日：2014-09-18

申请号：US13833691

申请日：2013-03-15

Applicant: LSI Corporation

Inventor： Stefan G. Block ,  Ting Zhou ,  Mikhail I. Grinchuk ,  Anatoli A. Bolotov ,  Lav D. Ivanovic

IPC: G11C7/10

CPC classification number: G11C7/1075 ,  G11C5/04

Abstract: A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request.

Abstract translation: 一种方法包括接收用于检索存储在三个存储器中的数据的多端口读取请求，每个存储器包括两个存储器模块和奇偶校验模块。 多端口读取请求与存储在第一存储器地址处的第一数据，存储在第二存储器地址的第二数据和存储在第三存储器地址的第三数据相关联。 当第一存储器地址，第二存储器地址和第三存储器地址与第一存储器模块相关联时，从第一存储器模块检索第一数据，使用来自第二存储器模块和第一奇偶校验模块的数据重建第二数据 并且使用来自第四存储器模块和第七存储器模块的数据来重建第三数据。 响应于多端口读取请求而提供第一数据，第二数据和第三数据。

公开(公告)号：US20140177324A1

公开(公告)日：2014-06-26

申请号：US13725028

申请日：2012-12-21

Applicant: LSI CORPORATION

Inventor： Sheng Liu ,  Ting Zhou

IPC: G11C8/16 ,  G11C11/00

CPC classification number: G11C8/16

Abstract: A storage device provides single-port read multiple-port write functionality and includes first and second memory arrays and a controller. The first memory array includes first and second single-port memory cells. The second single-port memory cell stores data in response to a memory access conflict associated with the first single-port memory cell. The second memory array stores location information associated with data stored in the first and second single-port memory cells. The controller is operatively coupled to the first and second memory arrays, and resolves the memory access conflict by determining locations to store data in the first and second single-port memory cells to thereby avoid a collision between concurrent memory accesses to the first single-port memory cell in response to the memory access conflict. The controller determines locations to store data in the first and second single-port memory cells based on the location information.

Abstract translation: 存储设备提供单端口读取多端口写入功能，并且包括第一和第二存储器阵列和控制器。 第一存储器阵列包括第一和第二单端口存储器单元。 响应于与第一单端口存储器单元相关联的存储器访问冲突，第二单端口存储器单元存储数据。 第二存储器阵列存储与存储在第一和第二单端口存储器单元中的数据相关联的位置信息。 控制器可操作地耦合到第一和第二存储器阵列，并且通过确定在第一和第二单端口存储器单元中存储数据的位置来解决存储器访问冲突，从而避免在对第一单端口的并行存储器访问之间的冲突 内存单元响应内存访问冲突。 控制器基于位置信息确定在第一和第二单端口存储器单元中存储数据的位置。