公开(公告)号：US12080580B2

公开(公告)日：2024-09-03

申请号：US17628776

申请日：2020-02-11

Applicant: LG ELECTRONICS INC.

Inventor： Hyunwoo Cho ,  Bongchu Shim ,  Hyeyoung Yang ,  Jisoo Ko ,  Wonjae Chang

IPC: H01L21/68 ,  H01L21/683 ,  H01L25/075 ,  H01L33/00

CPC classification number: H01L21/68 ,  H01L21/6833 ,  H01L21/6835 ,  H01L25/0753 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/0093 ,  H01L2221/68354 ,  H01L2221/68368

Abstract: The present invention provides an assembly substrate used in a method for manufacturing a display device which mounts semiconductor light emitting devices on a predetermined position of an assembly substrate by using an electric field and a magnetic field. Specifically, the assembly substrate is characterized by comprising: a base part; a plurality of assembly electrodes formed extending in one direction and disposed on the base part; a dielectric layer laminated on the base part so as to cover the assembly electrodes; a partition wall formed on the base part and including a plurality of grooves for guiding the semiconductor light emitting devices to a predetermined position; and a metal shielding layer formed on the base part, wherein each of the plurality of grooves penetrates the partition wall so as to form a seating surface on which the guided light emitting devices are seated, and the metal shielding layer overlaps with a part of the seating surface such that an electric field formed on a part of the seating surface is shielded.

公开(公告)号：US11133426B2

公开(公告)日：2021-09-28

申请号：US16457129

申请日：2019-06-28

Applicant: LG ELECTRONICS INC.

Inventor： Jungmin Ha ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn ,  Hyungwook Choi ,  Wonjae Chang ,  Jaesung Kim

IPC: H01L31/0224 ,  H01L31/0216 ,  H01L31/0747 ,  H01L31/02 ,  H01L31/0368 ,  H01L31/077 ,  H01L31/18

Abstract: A method for manufacturing a solar cell can include forming a tunneling layer on first and second surfaces of a semiconductor substrate, the tunneling layer including a dielectric material; forming a polycrystalline silicon layer on the tunnel layer at the first surface and on the second surface of the semiconductor substrate; removing portions of the tunnel layer and the polycrystalline silicon layer formed at the first surface of the semiconductor substrate; forming a doping region at the first surface of the semiconductor substrate by diffusing a dopant; forming a passivation layer on the polycrystalline silicon layer at the second surface of the semiconductor substrate; and forming a second electrode connected to the polycrystalline silicon layer by penetrating through the passivation layer.

公开(公告)号：US10230009B2

公开(公告)日：2019-03-12

申请号：US15995701

申请日：2018-06-01

Applicant: LG ELECTRONICS INC.

Inventor： Jungmin Ha ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn ,  Hyungwook Choi ,  Wonjae Chang ,  Jaesung Kim

IPC: H01L31/0216 ,  H01L31/0224 ,  H01L31/0747 ,  H01L31/02 ,  H01L31/0368 ,  H01L31/077 ,  H01L31/18

Abstract: A solar cell can include a silicon semiconductor substrate having a first conductive type; a oxide layer on a first surface of the silicon semiconductor substrate; a polysilicon layer on the oxide layer and having the first conductive type; an emitter region at a second surface of the silicon semiconductor substrate opposite to the first surface and having a second conductive type opposite to the first conductive type; a first passivation film on the polysilicon layer; a first electrode connected to the polysilicon layer through an opening formed in the first passivation film; a second passivation film on the emitter region; and a second electrode connected to the emitter region through an opening formed in the second passivation film.

公开(公告)号：US10566487B2

公开(公告)日：2020-02-18

申请号：US15196743

申请日：2016-06-29

Applicant: LG ELECTRONICS INC.

Inventor： Wonjae Chang ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn

IPC: H01L31/0745 ,  H01L31/0224 ,  H01L31/18 ,  H01L31/0288 ,  H01L31/0216 ,  H01L31/0236 ,  H01L31/0368

Abstract: Disclosed is a solar cell including a semiconductor substrate, and a dopant layer disposed over one surface of the semiconductor substrate and having a crystalline structure different from that of the semiconductor substrate, the dopant layer including a dopant. The dopant layer includes a plurality of semiconductor layers stacked one above another in a thickness direction thereof, and an interface layer interposed therebetween. The interface layer is an oxide layer having a higher concentration of oxygen than that in each of the plurality of semiconductor layers.

公开(公告)号：US10367115B2

公开(公告)日：2019-07-30

申请号：US15832321

申请日：2017-12-05

Applicant: LG ELECTRONICS INC.

Inventor： Juhwa Cheong ,  Junyong Ahn ,  Wonjae Chang ,  Jaesung Kim

IPC: H01L31/18 ,  H01L31/068 ,  H01L31/0368 ,  H01L31/0216 ,  H01L31/0236 ,  H01L31/024 ,  H01L31/0745 ,  H01L31/105 ,  H01L31/20 ,  H01L31/0224

Abstract: A method of manufacturing a solar cell can include forming a silicon oxide film on a semiconductor substrate and successively exposing the silicon oxide film to a temperature in a range of 570° C. to 700° C. to anneal the silicon oxide film.

公开(公告)号：US10014419B2

公开(公告)日：2018-07-03

申请号：US15643180

申请日：2017-07-06

Applicant: LG ELECTRONICS INC.

Inventor： Jungmin Ha ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn ,  Hyungwook Choi ,  Wonjae Chang ,  Jaesung Kim

IPC: H01L31/18 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/0747 ,  H01L31/02 ,  H01L31/0368 ,  H01L31/077

CPC classification number: H01L31/022433 ,  H01L31/0201 ,  H01L31/02167 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/03685 ,  H01L31/0747 ,  H01L31/077 ,  H01L31/1824 ,  H01L31/1864 ,  H01L31/1868 ,  Y02E10/50

Abstract: A method for manufacturing a solar cell can include a tunnel layer forming step of forming a tunnel layer on a first surface of a semiconductor substrate, a first conductive type semiconductor region forming step of forming a first conductive type semiconductor region on the first surface of the semiconductor substrate, a second conductive type semiconductor region forming step of forming a second conductive type semiconductor region by doping impurities of a second conductive type into a second surface of the semiconductor substrate, a first passivation film forming step of forming a first passivation film on the first conductive type semiconductor region and an electrode forming step of forming a first electrode connected to the first conductive type semiconductor region and a second electrode connected to the second conductive type semiconductor region.

公开(公告)号：US09722104B2

公开(公告)日：2017-08-01

申请号：US14953264

申请日：2015-11-27

Applicant: LG ELECTRONICS INC.

Inventor： Jungmin Ha ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn ,  Hyungwook Choi ,  Wonjae Chang ,  Jaesung Kim

IPC: H01L31/0216 ,  H01L31/0224 ,  H01L31/0747 ,  H01L31/02 ,  H01L31/0368 ,  H01L31/077 ,  H01L31/18

CPC classification number: H01L31/022433 ,  H01L31/0201 ,  H01L31/02167 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/03685 ,  H01L31/0747 ,  H01L31/077 ,  H01L31/1824 ,  H01L31/1864 ,  H01L31/1868 ,  Y02E10/50

Abstract: Disclosed are a solar cell and a method for manufacturing the same. A solar cell includes a semiconductor substrate, a tunnel layer on the first surface of the semiconductor substrate, a first conductive type semiconductor region on the tunnel layer and includes impurities of a first conductive type, a second conductive type semiconductor region on a second surface and includes impurities of a second conductive type opposite the first conductive type, a first passivation film on the first conductive type semiconductor region, a first electrode formed on the first passivation film and connected to the first conductive type semiconductor region through an opening portion formed in the first passivation film, a second passivation film on the second conductive type semiconductor region, and a second electrode formed on the second passivation film and connected to the second conductive type semiconductor region through an opening portion formed in the second passivation film.

公开(公告)号：US11462654B2

公开(公告)日：2022-10-04

申请号：US16504995

申请日：2019-07-08

Applicant: LG ELECTRONICS INC.

Inventor： Wonjae Chang ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn

IPC: H01L31/0745 ,  H01L31/0224 ,  H01L31/18 ,  H01L31/0288 ,  H01L31/0216 ,  H01L31/0236 ,  H01L31/0368

Abstract: Disclosed is a solar cell including a semiconductor substrate, and a dopant layer disposed over one surface of the semiconductor substrate and having a crystalline structure different from that of the semiconductor substrate, the dopant layer including a dopant. The dopant layer includes a plurality of semiconductor layers stacked one above another in a thickness direction thereof, and an interface layer interposed therebetween. The interface layer is an oxide layer having a higher concentration of oxygen than that in each of the plurality of semiconductor layers.

公开(公告)号：US11239379B2

公开(公告)日：2022-02-01

申请号：US16456915

申请日：2019-06-28

Applicant: LG ELECTRONICS INC.

Inventor： Jungmin Ha ,  Sungjin Kim ,  Juhwa Cheong ,  Junyong Ahn ,  Hyungwook Choi ,  Wonjae Chang ,  Jaesung Kim

IPC: H01L31/0224 ,  H01L31/0216 ,  H01L31/0747 ,  H01L31/02 ,  H01L31/0368 ,  H01L31/077 ,  H01L31/18

Abstract: A solar cell can include a silicon substrate; a tunnel layer disposed on a first surface of the silicon substrate, the tunnel layer including a dielectric material; a polycrystalline silicon layer disposed on the tunnel layer; a dielectric layer disposed on the polycrystalline silicon layer; and an electrode penetrating through the dielectric layer and directly contacting with the polycrystalline silicon layer, wherein the polycrystalline silicon layer includes a metal crystal region positioned at a region where the polycrystalline silicon layer contacts the electrode, and wherein the metal crystal region includes a plurality of metal crystals, the plurality of metal crystals including a metal material same as a metal material included in the electrode.

公开(公告)号：US10971646B2

公开(公告)日：2021-04-06

申请号：US16520014

申请日：2019-07-23

Applicant: LG ELECTRONICS INC.

Inventor： Wonjae Chang ,  Junyong Ahn ,  Hyunho Lee

IPC: H01L31/18 ,  C23C16/24 ,  C23C16/455 ,  C23C16/458

Abstract: Provided is a Chemical vapor deposition (CVD) equipment including a chamber having an inner space, a plurality of silicon wafers disposed in the inner space of the chamber in an upright position; and a plurality of shower nozzles configured to inject a mixed gas composed of a silicon deposition gas and an impurity gas toward each side edge of the plurality of wafers. The plurality of shower nozzles can be disposed at both sides of the plurality of the plurality of silicon wafers.