公开(公告)号：US11329640B1

公开(公告)日：2022-05-10

申请号：US17178633

申请日：2021-02-18

申请人： Keysight Technologies, Inc.

发明人： Charles Wu ,  Ken A. Nishimura ,  Kenneth D. Poulton

IPC分类号： H03K5/14 ,  G11C27/00 ,  G11C7/22 ,  G11C7/10 ,  H03K5/00

摘要： An analog delay line includes a clock generator, an analog sampling circuit, a bank of analog memory cells, a memory controller, an analog readout circuit, and an analog multiplexer. The clock generator is configured to output plural reception clock signals of different frequencies and plural transmission clock signals of different frequencies, the transmission clock signals offset in accumulated phase relative to the reception clock signals. The analog sampling circuit is controlled by at least one of the reception clock signals, and is configured to output a sequence of sampled voltages of an analog input signal. The memory controller is configured to control a write operation at a write frequency of at least one of the reception clock signals and a read operation at a read frequency of at least one of the transmission clock signals. The write operation is for sequentially storing the sampled voltages received from the analog sampling circuit in the bank of analog memory cells, and the read operation is for sequentially reading the sampled voltages from the bank of analog memory cells. The analog readout circuit is configured to buffer the sampled voltages read from the bank of analog memory cells. The analog multiplexer is controlled by at least one of the transmission clock signals, and is configured to multiplex the sampled voltages buffered by the readout circuit to generate an analog output signal. A sampling rate of the analog input signal is within a factor of 2 of a sampling rate of the analog output signal.

公开(公告)号：US10069505B1

公开(公告)日：2018-09-04

申请号：US15703401

申请日：2017-09-13

申请人： Keysight Technologies, Inc.

发明人： Kenneth D. Poulton ,  Robert Edward Jewett

IPC分类号： H03M1/06

摘要： A circuit for digital-to-analog conversion includes a first digital-to-analog converter (DAC), a second DAC, and an output node. The first DAC provides charges from multiple first charge sources segmented into a first group for most significant bits of a digital input to the first DAC and a second group for least significant bits of the digital input. Dither is both added to the digital input to the first DAC and used as sole digital input to the second DAC. Analog output from the second DAC is subtracted from analog output of the first DAC at the output node so as to cancel the dither added to the first DAC.