公开(公告)号：US20160377561A1

公开(公告)日：2016-12-29

申请号：US15166591

申请日：2016-05-27

Applicant: KLA-Tencor Corporation

Inventor： Vijayakumar Ramachandran ,  Ravikumar Sanapala ,  Vidyasagar Anantha ,  Philip Measor ,  Rajesh Manepalli ,  Jing Fang

IPC: G01N23/225 ,  G01N21/956 ,  G01N21/95

CPC classification number: G01N21/9501 ,  G01N21/95607 ,  G01N2021/8854 ,  G01N2021/95615 ,  G01N2223/6116 ,  G01N2223/646 ,  H01L22/12 ,  H01L22/20

Abstract: A defect inspection system includes an inspection sub-system and a controller communicatively coupled to the detector. The inspection sub-system includes an illumination source configured to generate a beam of illumination, a set of illumination optics to direct the beam of illumination to a sample, and a detector configured to collect illumination emanating from the sample. The controller includes a memory device and one or more processors configured to execute program instructions. The controller is configured to determine one or more target patterns corresponding to one or more features on the sample, define one or more care areas on the sample based on the one or more target patterns and design data of the sample stored within the memory device of the controller, and identify one or more defects within the one or more care areas of the sample based on the illumination collected by the detector.

Abstract translation: 缺陷检查系统包括检测子系统和通信地耦合到检测器的控制器。 检查子系统包括被配置为产生照射束的照明源，一组用于将照射束引导到样本的照明光学器件，以及被配置为收集从样品发出的照明的检测器。 控制器包括存储器设备和被配置为执行程序指令的一个或多个处理器。 控制器被配置为确定与样本上的一个或多个特征相对应的一个或多个目标模式，基于存储在存储器装置内的样本的一个或多个目标模式和样本的设计数据来定义样本上的一个或多个保养区域 控制器，并且基于由检测器收集的照明来识别样品的一个或多个护理区域内的一个或多个缺陷。

公开(公告)号：US20180149603A1

公开(公告)日：2018-05-31

申请号：US15826019

申请日：2017-11-29

Applicant: KLA-Tencor Corporation

Inventor： Santosh Bhattacharyya ,  Devashish Sharma ,  Christopher Maher ,  Bo Hua ,  Philip Measor ,  Robert M. Danen

IPC: G01N21/95 ,  G01N23/04 ,  G01R31/28 ,  G06T7/00

CPC classification number: G01N21/9505 ,  G01N21/956 ,  G01N23/04 ,  G01N2021/8883 ,  G01N2223/6462 ,  G01R31/2831 ,  G01R31/311 ,  G06T7/001 ,  G06T2207/10061 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148

Abstract: Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.

公开(公告)号：US20180025952A1

公开(公告)日：2018-01-25

申请号：US15390473

申请日：2016-12-24

Applicant: KLA-Tencor Corporation

Inventor： Philip Measor ,  Robert Danen ,  Paul MacDonald

IPC: H01L21/66 ,  G01R31/28 ,  H01L21/306

CPC classification number: H01L22/22 ,  G01R31/2898 ,  H01L21/30608 ,  H01L21/30625 ,  H01L22/12 ,  H01L22/24 ,  H01L27/11582

Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

公开(公告)号：US11047806B2

公开(公告)日：2021-06-29

申请号：US15826019

申请日：2017-11-29

Applicant: KLA-Tencor Corporation

Inventor： Santosh Bhattacharyya ,  Devashish Sharma ,  Christopher Maher ,  Bo Hua ,  Philip Measor ,  Robert M. Danen

IPC: G06K9/00 ,  G01N21/95 ,  G01R31/311 ,  G01N21/956 ,  G01N23/04 ,  G01R31/28 ,  G06T7/00 ,  G01N21/88

Abstract: Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.

公开(公告)号：US10887580B2

公开(公告)日：2021-01-05

申请号：US15683077

申请日：2017-08-22

Applicant: KLA-Tencor Corporation

Inventor： Pavel Kolchin ,  Robert M. Danen ,  Philip Measor

IPC: H04N13/254 ,  H04N13/221 ,  G06K9/20 ,  G06T5/50 ,  G06T7/00 ,  G01N21/956 ,  H04N13/271 ,  G01N21/95 ,  G01N21/88 ,  G06T7/70 ,  G01N21/84 ,  G06K9/40 ,  G06K9/62

Abstract: Methods and systems for improved detection and classification of defects of interest (DOI) on semiconductor wafers based on three-dimensional images are described herein. Three dimensional imaging of volumes of thick, layered structures enables accurate defect detection and estimation of defect location in three dimensions at high throughput. A series of images are acquired at a number of different wafer depths. A three dimensional image of a thick semiconductor structure is generated from the series of images. Defects are identified and classified based on an analysis of the three dimensional image of the thick semiconductor structure. In some examples, the three-dimensional image stack is visualized by contour plots or cross-sectional plots to identify a characteristic defect response. In some examples, the three-dimensional image is processed algorithmically to identify and classify defects. In another aspect, the location of a defect is estimated in three dimensions based on the three dimensional image.

公开(公告)号：US20180103247A1

公开(公告)日：2018-04-12

申请号：US15683077

申请日：2017-08-22

Applicant: KLA-Tencor Corporation

Inventor： Pavel Kolchin ,  Robert M. Danen ,  Philip Measor

IPC: H04N13/02 ,  G01N21/95

CPC classification number: H04N13/254 ,  G01N21/9505 ,  G01N21/956 ,  G01N2021/8438 ,  G01N2021/8861 ,  G06K9/2027 ,  G06K9/40 ,  G06K9/6267 ,  G06T5/50 ,  G06T7/0004 ,  G06T7/0008 ,  G06T7/70 ,  G06T2207/10028 ,  G06T2207/10148 ,  G06T2207/20221 ,  G06T2207/30148 ,  H04N13/221 ,  H04N13/271

Abstract: Methods and systems for improved detection and classification of defects of interest (DOI) on semiconductor wafers based on three-dimensional images are described herein. Three dimensional imaging of volumes of thick, layered structures enables accurate defect detection and estimation of defect location in three dimensions at high throughput. A series of images are acquired at a number of different wafer depths. A three dimensional image of a thick semiconductor structure is generated from the series of images. Defects are identified and classified based on an analysis of the three dimensional image of the thick semiconductor structure. In some examples, the three-dimensional image stack is visualized by contour plots or cross-sectional plots to identify a characteristic defect response. In some examples, the three-dimensional image is processed algorithmically to identify and classify defects. In another aspect, the location of a defect is estimated in three dimensions based on the three dimensional image.

公开(公告)号：US10928740B2

公开(公告)日：2021-02-23

申请号：US15830232

申请日：2017-12-04

Applicant: KLA-Tencor Corporation

Inventor： Philip Measor ,  Robert M. Danen

IPC: G03F7/20 ,  G03F7/00 ,  G03F1/84 ,  H01J37/28 ,  G01N21/95 ,  H01L21/67 ,  H01L21/66 ,  G01N21/93 ,  G01N21/956

Abstract: A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.

公开(公告)号：US10249546B2

公开(公告)日：2019-04-02

申请号：US15390473

申请日：2016-12-24

Applicant: KLA-Tencor Corporation

Inventor： Philip Measor ,  Robert Danen ,  Paul MacDonald

IPC: H01L21/66 ,  H01L21/306 ,  G01R31/28 ,  H01L27/11582

Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

公开(公告)号：US20180224749A1

公开(公告)日：2018-08-09

申请号：US15830232

申请日：2017-12-04

Applicant: KLA-Tencor Corporation

Inventor： Philip Measor ,  Robert M. Danen

IPC: G03F7/20 ,  G03F7/00 ,  G03F1/84 ,  H01J37/28 ,  G01N21/95 ,  H01L21/67 ,  H01L21/66

CPC classification number: G03F7/7065 ,  G01N21/93 ,  G01N21/9501 ,  G01N21/9503 ,  G01N21/95607 ,  G03F1/84 ,  G03F7/0037 ,  H01J37/28 ,  H01J2237/2817 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/26

Abstract: A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.

公开(公告)号：US10018571B2

公开(公告)日：2018-07-10

申请号：US15166591

申请日：2016-05-27

Applicant: KLA-Tencor Corporation

Inventor： Vijayakumar Ramachandran ,  Ravikumar Sanapala ,  Vidyasagar Anantha ,  Philip Measor ,  Rajesh Manepalli ,  Jing Fang

IPC: G01N23/225 ,  G01N21/956 ,  G01N21/95 ,  H01L21/66 ,  G01N21/88

CPC classification number: G01N21/9501 ,  G01N21/95607 ,  G01N2021/8854 ,  G01N2021/95615 ,  G01N2223/6116 ,  G01N2223/646 ,  H01L22/12 ,  H01L22/20

Abstract: A defect inspection system includes an inspection sub-system and a controller communicatively coupled to the detector. The inspection sub-system includes an illumination source configured to generate a beam of illumination, a set of illumination optics to direct the beam of illumination to a sample, and a detector configured to collect illumination emanating from the sample. The controller includes a memory device and one or more processors configured to execute program instructions. The controller is configured to determine one or more target patterns corresponding to one or more features on the sample, define one or more care areas on the sample based on the one or more target patterns and design data of the sample stored within the memory device of the controller, and identify one or more defects within the one or more care areas of the sample based on the illumination collected by the detector.