知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.021 秒)

    METHOD FOR FORMING TRENCHES IN A SEMICONDUCTOR COMPONENT
    1.
    发明申请
    METHOD FOR FORMING TRENCHES IN A SEMICONDUCTOR COMPONENT 有权
    在半导体元件中形成铁素体的方法

    公开(公告)号：US20110169125A1

    公开(公告)日：2011-07-14

    申请号：US13004599

    申请日：2011-01-11

    申请人： Jochen REINMUTH ,  Barbara Will ,  Heribert Weber

    发明人： Jochen REINMUTH ,  Barbara Will ,  Heribert Weber

    IPC分类号： H01L29/06 ,  H01L21/60

    CPC分类号： H01L21/3081 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C1/00404 ,  B81C1/00626 ,  H01L21/0334 ,  H01L21/76229

    摘要： A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.

    摘要翻译： 描述了一种用于在半导体部件，特别是微机电或电半导体部件中形成至少一个凹部的方法，其具有以下步骤：将至少一个掩模施加到半导体部件，形成至少一个具有至少一个或多个 在要形成的凹部上的掩模中的格子孔，形成作为蚀刻速率和/或要形成的凹部的尺寸的函数的格子孔或格子孔; 在网格下面形成凹陷。

    Method for forming trenches in a semiconductor component
    2.
    发明授权
    Method for forming trenches in a semiconductor component 有权
    在半导体部件中形成沟槽的方法

    公开(公告)号：US08679975B2

    公开(公告)日：2014-03-25

    申请号：US13004599

    申请日：2011-01-11

    申请人： Jochen Reinmuth ,  Barbara Will ,  Heribert Weber

    发明人： Jochen Reinmuth ,  Barbara Will ,  Heribert Weber

    IPC分类号： H01L21/60

    CPC分类号： H01L21/3081 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C1/00404 ,  B81C1/00626 ,  H01L21/0334 ,  H01L21/76229

    摘要： A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.

    摘要翻译： 描述了一种用于在半导体部件，特别是微机电或电半导体部件中形成至少一个凹部的方法，其具有以下步骤：将至少一个掩模施加到半导体部件，形成至少一个具有至少一个或多个 在要形成的凹部上的掩模中的格子孔，形成作为蚀刻速率和/或要形成的凹部的尺寸的函数的格子孔或格子孔; 在网格下面形成凹陷。

    Method for producing highly doped semiconductor components
    4.
    发明授权
    Method for producing highly doped semiconductor components 失效
    高掺杂半导体元件的制造方法

    公开(公告)号：US06806173B1

    公开(公告)日：2004-10-19

    申请号：US09914404

    申请日：2001-12-13

    申请人： Richard Spitz ,  Alfred Goerlach ,  Barbara Will ,  Helga Uebbing ,  Roland Riekert ,  Christian Adamski

    发明人： Richard Spitz ,  Alfred Goerlach ,  Barbara Will ,  Helga Uebbing ,  Roland Riekert ,  Christian Adamski

    IPC分类号： H01L2124

    CPC分类号： H01L29/66136 ,  H01L21/2255

    摘要： A method is proposed for producing semiconductor components, in which at least one doped region is introduced in a wafer, a solid glass layer provided with dopant being applied on at least one of the two sides of a semiconductor wafer, in another step, the wafer being heated to high temperatures so that the dopant from the glass layer penetrates deep into the wafer to produce the at least one doped region; and in a further step, the glass layer being removed. The method is used for producing homogeneous, heavily doped regions, it also being possible to introduce these regions in the wafer on both sides and for the regions to be of different doping type.

    摘要翻译： 提出一种用于制造其中在晶片中引入至少一个掺杂区域的半导体组件的方法，在半导体晶片的两侧中的至少一个上设置掺杂剂的固体玻璃层，在另一步骤中，晶片 被加热到高温，使得来自玻璃层的掺杂剂深入到晶片中以产生至少一个掺杂区域; 并且在另一步骤中，去除玻璃层。 该方法用于生产均匀的重掺杂区域，也可以在两侧的晶片中引入这些区域，并且可以将区域引入具有不同掺杂类型的区域。

    Semiconductor system having a pn transition and method for manufacturing a semiconductor system
    5.
    发明授权
    Semiconductor system having a pn transition and method for manufacturing a semiconductor system 有权
    具有pn跃迁的半导体系统和用于制造半导体系统的方法

    公开(公告)号：US07199031B2

    公开(公告)日：2007-04-03

    申请号：US10501287

    申请日：2002-11-19

    申请人： Maria Del Rocio Martin Lopez ,  Richard Spitz ,  Alfred Goerlach ,  Barbara Will

    发明人： Maria Del Rocio Martin Lopez ,  Richard Spitz ,  Alfred Goerlach ,  Barbara Will

    IPC分类号： H01L21/22

    CPC分类号： H01L29/66106 ,  H01L29/866 ,  Y10S438/965

    摘要： A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivity type and a second layer of a second conductivity type, which is of opposite polarity to the first conductivity type. The first layer has an edge region and a center region, the pn transition being provided between the first layer and the second layer. The second layer is more weakly doped in its edge region than in its center region, and the boundary surface of the pn transition at the edge region is non-parallel to the main chip plane.

    摘要翻译： 公开了具有pn跃迁的半导体系统和制造半导体系统的方法。 半导体系统被设计为具有边缘区域的芯片的形式，该半导体系统包括第一导电类型的第一层和与第一导电类型相反极性的第二导电类型的第二层。 第一层具有边缘区域和中心区域，pn跃迁设置在第一层和第二层之间。 第二层在其边缘区域比在其中心区域更弱地掺杂，边缘区域的pn跃迁的边界表面不平行于主芯片平面。

    Single-phase converter module
    6.
    发明申请
    Single-phase converter module 审中-公开
    单相转换器模块

    公开(公告)号：US20060124957A1

    公开(公告)日：2006-06-15

    申请号：US10538269

    申请日：2003-06-12

    申请人： Stefan Hornung ,  Peter Urbach ,  Barbara Will

    发明人： Stefan Hornung ,  Peter Urbach ,  Barbara Will

    IPC分类号： H01L29/74

    CPC分类号： H01L25/074 ,  H01L23/49562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A converter module is described having a positive terminal (2), a negative terminal (4), and a phase terminal (3), as well as a first semiconductor chip (9) and a second semiconductor chip (9), the terminals (2-4) and the semiconductor chips (9) being situated on top of one another in a stack. A particularly simple and cost-effective converter module may produced in that the positive terminal (2), the negative terminal (4), or the phase terminal (3) are made up of a contact plate (5), including a bar-shaped terminal lug (6) which is positioned asymmetrically on the contact plate (5), and an auxiliary element (7) is provided at its end which prevents the terminal (2-4) from tilting.

    摘要翻译： A转换器模块被描述为具有正端子（2），负端子（4）和相位端子（3），以及第一半导体芯片（9）和第二半导体芯片（9），端子 2 - 4），并且半导体芯片（9）在堆叠中彼此位于顶部。 可以产生一种特别简单且具有成本效益的转换器模块，其中正极端子（2），负极端子（4）或相位端子（3）由接触板（5）构成，该接触板包括棒状 在所述接触板（5）上不对称地定位的端子凸耳（6），并且在其端部设置辅助元件（7），以防止所述端子（2 - 4）倾斜。

    Semiconductor arrangement comprising a pn-transition and method for producing a semiconductor arrangement
    7.
    发明申请
    Semiconductor arrangement comprising a pn-transition and method for producing a semiconductor arrangement 有权
    包括pn跃迁的半导体装置和用于制造半导体装置的方法

    公开(公告)号：US20050121690A1

    公开(公告)日：2005-06-09

    申请号：US10501287

    申请日：2002-11-19

    申请人： Maria Lopez ,  Richard Spitz ,  Alfred Goerlach ,  Barbara Will

    发明人： Maria Lopez ,  Richard Spitz ,  Alfred Goerlach ,  Barbara Will

    IPC分类号： H01L21/329 ,  H01L29/866 ,  H01L29/32 ,  H01L21/336 ,  H01L29/74 ,  H01L31/111

    CPC分类号： H01L29/66106 ,  H01L29/866 ,  Y10S438/965

    摘要： A semiconductor system having a pn transition and a method for manufacturing a semiconductor system are disclosed. The semiconductor system is designed in the form of a chip having an edge region, the semiconductor system includes a first layer of a first conductivity type and a second layer of a second conductivity type, which is of opposite polarity to the first conductivity type. The first layer has an edge region and a center region, the pn transition being provided between the first layer and the second layer. The second layer is more weakly doped in its edge region than in its center region, and the boundary surface of the pn transition at the edge region is non-parallel to the main chip plane.

    摘要翻译： 公开了具有pn跃迁的半导体系统和制造半导体系统的方法。 半导体系统被设计为具有边缘区域的芯片的形式，该半导体系统包括第一导电类型的第一层和与第一导电类型相反极性的第二导电类型的第二层。 第一层具有边缘区域和中心区域，pn跃迁设置在第一层和第二层之间。 第二层在其边缘区域比在其中心区域更弱地掺杂，边缘区域的pn跃迁的边界表面不平行于主芯片平面。