公开(公告)号：US08278122B2

公开(公告)日：2012-10-02

申请号：US12696771

申请日：2010-01-29

Applicant: Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

Inventor： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L21/00

CPC classification number: H01L43/12 ,  H01L27/222

Abstract: A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

Abstract translation: 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。

公开(公告)号：US20110189796A1

公开(公告)日：2011-08-04

申请号：US12696771

申请日：2010-01-29

Applicant: Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

Inventor： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222

Abstract: A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

Abstract translation: 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。

公开(公告)号：US20140061738A1

公开(公告)日：2014-03-06

申请号：US13602494

申请日：2012-09-04

Applicant: Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

Inventor： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

IPC: H01L31/0216

CPC classification number: H01L21/266 ,  H01L27/14689

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract translation: 本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。 使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。 三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层， 面具。 形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。

公开(公告)号：US08759225B2

公开(公告)日：2014-06-24

申请号：US13602494

申请日：2012-09-04

Applicant: Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

Inventor： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

IPC: H01L21/311

CPC classification number: H01L21/266 ,  H01L27/14689

Abstract: The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

Abstract translation: 本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。 使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。 三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层， 面具。 形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。

公开(公告)号：US10553785B2

公开(公告)日：2020-02-04

申请号：US13452230

申请日：2012-04-20

Applicant: Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

Inventor： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

Abstract: This description relates to a method for fabricating a magnetoresistive random access memory (MRAM) device having a plurality of magnetic tunnel junction (MTJ) units. The method includes forming a bottom conductive layer, forming an anti-ferromagnetic layer and forming a tunnel layer over the bottom conductive layer and the anti-ferromagnetic layer. The method further includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer and forming a top conductive layer over the free magnetic layer. The method further includes performing at least one lithographic process to remove portions of the bottom conductive layer, the anti-ferromagnetic layer, the tunnel layer, the free magnetic layer and the top conductive layer that is uncovered by the photoresist layer until the bottom conductive layer is exposed and removing portions of at least one sidewall of the MTJ unit.

公开(公告)号：US08629531B2

公开(公告)日：2014-01-14

申请号：US13030645

申请日：2011-02-18

Applicant: Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L21/20 ,  H01L21/18

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

Abstract translation: 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

公开(公告)号：US08569849B2

公开(公告)日：2013-10-29

申请号：US13618908

申请日：2012-09-14

Applicant: Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

Inventor： Wei-Hang Huang ,  Shih-Chang Liu ,  Chern-Yow Hsu ,  Fu-Ting Sung ,  Chia-Shiung Tsai

IPC: H01L29/82

CPC classification number: H01L43/12 ,  G11C11/16

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract translation: 提供半导体器件和制造方法，例如MTJ器件和制造MTJ器件的方法。 MTJ装置可以包括底部电极，MTJ堆叠和顶部电极，其中顶部电极使用填充孔技术形成。 顶部电极可以具有倾斜的侧壁。 可以通过沉积相应的MTJ层来形成MTJ堆叠。 可以在MTJ层上形成并图案化图案化掩模以形成限定顶部电极的开口。 开口填充有导电材料以形成顶部电极。 然后将顶部电极用作掩模以对MTJ层进行图案化，从而形成MTJ堆叠。

公开(公告)号：US20130026585A1

公开(公告)日：2013-01-31

申请号：US13190966

申请日：2011-07-26

Applicant: Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

Inventor： Fu-Ting Sung ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L29/82 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

公开(公告)号：US20120211759A1

公开(公告)日：2012-08-23

申请号：US13030645

申请日：2011-02-18

Applicant: Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Ming Chyi Liu ,  Hsieh Ching Pei ,  Jiun-Lei Yu ,  Chi-Ming Chen ,  Shih-Chang Liu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/107 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/007 ,  H01L33/12

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.

Abstract translation: 本公开提供了一种半导体结构。 所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

公开(公告)号：US08227850B2

公开(公告)日：2012-07-24

申请号：US12723381

申请日：2010-03-12

Applicant: Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

Inventor： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC: H01L29/76

CPC classification number: H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract translation: 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。