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    Methods of manufacturing reference sample substrates for analyzing metal contamination levels
    1.
    发明申请
    Methods of manufacturing reference sample substrates for analyzing metal contamination levels 有权
    制造用于分析金属污染水平的参考样品基板的方法

    公开(公告)号：US20070172952A1

    公开(公告)日：2007-07-26

    申请号：US11646142

    申请日：2006-12-27

    申请人： Jae-Seok Lee ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Mi-Ae Kim

    发明人： Jae-Seok Lee ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Mi-Ae Kim

    IPC分类号： G01N31/00

    CPC分类号： G01N23/2258 ,  Y10T436/108331

    摘要： A method of manufacturing a reference sample substrate for analyzing a metal contamination level includes coating an organic silica solution including metal impurities on a semiconductor substrate and forming an oxide layer on the semiconductor substrate by thermally treating the semiconductor substrate having the coated organic silica solution. The metal impurities are substantially uniformly distributed in the oxide layer and the metal impurities are positioned at predetermined portions of the oxide layer.

    摘要翻译： 制造用于分析金属污染水平的参考样品基材的方法包括在半导体衬底上涂覆包含金属杂质的有机二氧化硅溶液，并通过热处理具有涂覆的有机二氧化硅溶液的半导体衬底，在半导体衬底上形成氧化物层。 金属杂质基本均匀分布在氧化物层中，金属杂质位于氧化物层的预定部分。

    Methods of manufacturing reference sample substrates for analyzing metal contamination levels
    2.
    发明授权
    Methods of manufacturing reference sample substrates for analyzing metal contamination levels 有权
    制造用于分析金属污染水平的参考样品基板的方法

    公开(公告)号：US07811836B2

    公开(公告)日：2010-10-12

    申请号：US11646142

    申请日：2006-12-27

    申请人： Jae-Seok Lee ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Mi-Ae Kim

    发明人： Jae-Seok Lee ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Mi-Ae Kim

    IPC分类号： H01L21/00

    CPC分类号： G01N23/2258 ,  Y10T436/108331

    摘要： A method of manufacturing a reference sample substrate for analyzing a metal contamination level includes coating an organic silica solution including metal impurities on a semiconductor substrate and forming an oxide layer on the semiconductor substrate by thermally treating the semiconductor substrate having the coated organic silica solution. The metal impurities are substantially uniformly distributed in the oxide layer and the metal impurities are positioned at predetermined portions of the oxide layer.

    摘要翻译： 制造用于分析金属污染水平的参考样品基材的方法包括在半导体衬底上涂覆包含金属杂质的有机二氧化硅溶液，并通过热处理具有涂覆的有机二氧化硅溶液的半导体衬底，在半导体衬底上形成氧化物层。 金属杂质基本均匀分布在氧化物层中，金属杂质位于氧化物层的预定部分。

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120196439A1

    公开(公告)日：2012-08-02

    申请号：US13289107

    申请日：2011-11-04

    申请人： Kook-Joo KIM ,  Jin-Ho Kim ,  Seung-Ki Chae ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Gyoung-Eun Byun

    发明人： Kook-Joo KIM ,  Jin-Ho Kim ,  Seung-Ki Chae ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Gyoung-Eun Byun

    IPC分类号： H01L21/28

    CPC分类号： H01L23/522 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.

    摘要翻译： 在形成半导体器件的导电图案结构的方法中，在基板上形成第一绝缘中间层。 形成第一布线以通过第一绝缘中间层。 在第一绝缘中间层上依次形成蚀刻停止层和第二绝缘中间层。 形成第二布线以通过第二绝缘中间层和蚀刻停止层。 在形成第二布线的同时，形成虚设图形以通过第二绝缘层和蚀刻停止层。 第二布线电连接到第一布线。 虚设图案与第二布线电隔离。

    Semiconductor devices and methods of manufacturing the same
    4.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08455359B2

    公开(公告)日：2013-06-04

    申请号：US13289107

    申请日：2011-11-04

    申请人： Kook-Joo Kim ,  Jin-Ho Kim ,  Seung-Ki Chae ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Gyoung-Eun Byun

    发明人： Kook-Joo Kim ,  Jin-Ho Kim ,  Seung-Ki Chae ,  Pil-Kwon Jun ,  Sun-Hee Park ,  Gyoung-Eun Byun

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L23/522 ,  H01L21/76829 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.

    摘要翻译： 在形成半导体器件的导电图案结构的方法中，在基板上形成第一绝缘中间层。 形成第一布线以通过第一绝缘中间层。 在第一绝缘中间层上依次形成蚀刻停止层和第二绝缘中间层。 形成第二布线以通过第二绝缘中间层和蚀刻停止层。 在形成第二布线的同时，形成虚设图形以通过第二绝缘层和蚀刻停止层。 第二布线电连接到第一布线。 虚设图案与第二布线电隔离。

    METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING COMPOSITIONS FOR ETCHING COPPER
    7.
    发明申请
    METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING COMPOSITIONS FOR ETCHING COPPER 有权
    使用组合物制造半导体器件以蚀刻铜的方法

    公开(公告)号：US20110130000A1

    公开(公告)日：2011-06-02

    申请号：US12948331

    申请日：2010-11-17

    申请人： Jung-Dae PARK ,  Da-Hee Lee ,  Seung-Ki Chae ,  Pil-Kwon Jun ,  Kwang-Shin Lim

    发明人： Jung-Dae PARK ,  Da-Hee Lee ,  Seung-Ki Chae ,  Pil-Kwon Jun ,  Kwang-Shin Lim

    IPC分类号： H01L21/60

    CPC分类号： H01L21/32134 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device includes preparing a substrate on which a fuze line containing copper is formed. The method further includes cutting the fuze line by emitting a laser beam, and applying a composition for etching copper to the substrate to finely etch a cutting area of the fuze line and to substantially remove at least one of a copper residue and a copper oxide residue remaining near the cutting area. The composition for etching copper includes about 0.01 to about 10 percent by weight of an organic acid, about 0.01 to 1.0 percent by weight of an oxidizing agent, and a protic solvent.

    摘要翻译： 制造半导体器件的方法包括制备其上形成有铜的引线的衬底。 该方法还包括通过发射激光束切割引信线，以及将用于蚀刻铜的组合物施加到基底上，以精细蚀刻引信线的切割区域并基本上除去铜残留物和氧化铜残留物中的至少一种 保留在切割区附近。 用于蚀刻铜的组合物包括约0.01至约10重量％的有机酸，约0.01至1.0重量％的氧化剂和质子溶剂。

    Wafer guides for processing semiconductor substrates
    9.
    发明授权
    Wafer guides for processing semiconductor substrates 失效
    用于处理半导体衬底的晶片导板

    公开(公告)号：US06959823B2

    公开(公告)日：2005-11-01

    申请号：US10619999

    申请日：2003-07-14

    申请人： Pil-Kwon Jun ,  Sang-oh Park ,  Yong-Kyun Ko ,  Hun-Jung Yi

    发明人： Pil-Kwon Jun ,  Sang-oh Park ,  Yong-Kyun Ko ,  Hun-Jung Yi

    IPC分类号： H01L21/304 ,  B65D25/10 ,  H01L21/00 ,  H01L21/673 ,  A47G19/08

    CPC分类号： H01L21/67326 ,  B65D25/103 ,  H01L21/67057 ,  Y10S134/902

    摘要： A wafer guide includes a horizontal support panel and at least three vertical panels attached on one surface of the support panel. Each of the vertical panels has a vertical body panel and a plurality of protrusions upwardly extended from a top surface of the vertical body panel. Gap regions between the protrusions act as slots for holding wafers. Sidewalls of the slots have a convex shaped profile when viewed from a top view, and bottom surfaces of the slots also have a convex shaped profile when viewed from a cross sectional view that crosses the vertical panels.

    摘要翻译： 晶片引导件包括水平支撑板和附接在支撑板的一个表面上的至少三个垂直板。 每个垂直面板具有垂直的主体面板和从垂直主体面板的顶面向上延伸的多个突起。 突起之间的间隙区域用作保持晶片的槽。 当从顶视图观察时，槽的侧壁具有凸形的轮廓，并且当从横切垂直板的横截面视图观察时，槽的底表面也具有凸形轮廓。

    Composition for removing photoresist, method of removing photoresist and method of manufacturing a semiconductor device using the same
    10.
    发明授权
    Composition for removing photoresist, method of removing photoresist and method of manufacturing a semiconductor device using the same 有权
    用于除去光致抗蚀剂的组合物，去除光致抗蚀剂的方法及使用其制造半导体器件的方法

    公开(公告)号：US07678751B2

    公开(公告)日：2010-03-16

    申请号：US11296000

    申请日：2005-12-06

    申请人： Jung-Dae Park ,  Sang-Eon Lee ,  Sang-Mun Chon ,  Yang-Koo Lee ,  Dong-Chul Heo ,  Pil-Kwon Jun

    发明人： Jung-Dae Park ,  Sang-Eon Lee ,  Sang-Mun Chon ,  Yang-Koo Lee ,  Dong-Chul Heo ,  Pil-Kwon Jun

    IPC分类号： C11D7/50

    CPC分类号： C11D7/264 ,  C11D7/5009 ,  C11D7/5013 ,  C11D7/5022 ,  C11D11/0047

    摘要： Disclosed are a composition for removing photoresist, a method of removing photoresist and a method of manufacturing a semiconductor device using a composition. The composition may include a ketone compound and a first polar aprotic solvent. The composition may also include the ketone compound and a second polar aprotic solvent. Moreover, the composition may include the first polar aprotic solvent and a second polar aprotic solvent with or without the ketone compound. The first polar aprotic solvent has at least one of an ether compound and an ester compound, and the second polar aprotic solvent has at least one of a sulfur-containing compound and a nitrogen-containing compound.

    摘要翻译： 公开了除去光致抗蚀剂的组合物，去除光刻胶的方法以及使用组合物制造半导体器件的方法。 组合物可以包括酮化合物和第一极性非质子溶剂。 组合物还可以包括酮化合物和第二极性非质子溶剂。 此外，组合物可以包括第一极性非质子溶剂和具有或不具有酮化合物的第二极性非质子溶剂。 第一极性非质子溶剂具有醚化合物和酯化合物中的至少一种，第二极性非质子溶剂具有含硫化合物和含氮化合物中的至少一种。