公开(公告)号：US20080103642A1

公开(公告)日：2008-05-01

申请号：US11899001

申请日：2007-08-29

Applicant: Isaiah Cox ,  Joseph Cox ,  Jonathan Edelson

Inventor： Isaiah Cox ,  Joseph Cox ,  Jonathan Edelson

IPC: G06G7/78 ,  G05D1/00

CPC classification number: G08G5/065

Abstract: A system for minimizing damage on collision to a vehicle having at least one self-propelled wheel is disclosed. The system comprises a motor in a wheel of said vehicle which drives the vehicle, means for measuring the speed of said wheel, means for measuring the torque of said motor, means for monitoring the ratio of the torque of the motor to the speed of the wheel, and means for stopping said motor when torque:speed ratio exceeds an acceptable value.

Abstract translation: 公开了一种用于使具有至少一个自推进轮的车辆的碰撞损伤最小化的系统。 该系统包括驱动车辆的所述车辆的车轮中的电动机，用于测量所述车轮的速度的装置，用于测量所述电动机的转矩的装置，用于监测电动机的转矩与所述电动机的转速的比率的装置 车轮以及当转矩比超过可接受值时停止所述电动机的装置。

公开(公告)号：US5887146A

公开(公告)日：1999-03-23

申请号：US695556

申请日：1996-08-12

Applicant: William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

Inventor： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC: G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F13/00 ,  G06F1/12

CPC classification number: G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Abstract translation: 基于硬件体系结构的非常快速，高效，高度可扩展，高效率的CCNUMA处理系统，可最大限度地减少系统总线争用，通过维护强大的排序和避免重试来最大化处理进度，并实现全映射目录结构高速缓存一致性协议。 缓存相干非均匀存储器访问（CCNUMA）架构在包括由主板和两个子板组成的多个集成模块的系统中实现。 插入主板的子板每个都包含两个作业处理器（JP），高速缓存和输入/输出（I / O）功能。 直接位于主板上的是两个小型计算机系统接口（SCSI）和一个局域网（LAN）接口形式的附加集成I / O功能。 主板包括主存储器，存储器控制器（MC）和用于高速缓存一致性的目录DRAM。 主板还包括GTL背板接口逻辑，系统时钟生成和分配逻辑，以及包括用于系统初始化的微控制器的本地资源。 交叉开关将各种逻辑块连接在一起。 一个完整的主板包含2个JP子板，2个PCI扩展板和最多512 MB的主内存。 每个子板包含两个50MHz的Motorola 88110 JP复合体，具有相关联的88410缓存控制器和1MB 2级缓存。 还提供单个16 MB的第三级直写缓存，并由第三级缓存控制器控制。

公开(公告)号：US20150129712A1

公开(公告)日：2015-05-14

申请号：US13526483

申请日：2012-06-18

Applicant: Isaiah W. Cox ,  Joseph Cox ,  Jan Vana ,  Joseph Goldman

Inventor： Isaiah W. Cox ,  Joseph Cox ,  Jan Vana ,  Joseph Goldman

IPC: B64C25/40 ,  G08G5/00

CPC classification number: B64C25/405 ,  G08G5/0021 ,  Y02T50/823

Abstract: A method for improving airport and ramp throughput is provided. The method minimizes the time interval between an aircraft's landing and takeoff by independently moving the aircraft with an onboard electric driver that drives at least one of the aircraft's wheels on the ground without the aircraft's engines. Turnaround time and aircraft idle time are reduced by eliminating engine operation while the aircraft is moving in the ramp area. The time between when an aircraft is not moving between pushback and taxi forward is substantially eliminated, leading to more efficient ramp operations as ramp space is freed for through traffic.

Abstract translation: 提供了一种改善机场和坡道吞吐量的方法。 该方法通过独立地使飞机与飞行器上的电动驾驶员独立地移动飞行器着陆和起飞之间的时间间隔最小化，而不用飞机的发动机驱动飞机的至少一个飞轮的地面。 当飞机在斜坡区域移动时，通过消除发动机运转，减少了周转时间和飞机空转时间。 飞机在推回和出租车前方之间的移动之间的时间基本上消除了，导致更高效的斜坡操作，因为通过交通释放了斜坡空间。

公开(公告)号：US20080059278A1

公开(公告)日：2008-03-06

申请号：US11565677

申请日：2006-12-01

Applicant: Steven Medina ,  Joseph Cox ,  Kenneth Marr

Inventor： Steven Medina ,  Joseph Cox ,  Kenneth Marr

IPC: G06F9/46

CPC classification number: G06Q10/06 ,  G06Q10/063112 ,  G06Q10/063116

Abstract: A system, method, and computer readable medium for offering uptime adjustments to a work schedule for at least one currently unscheduled agent possessing at least one skill type, that comprises, accepting at least one forecasted manpower requirement of zero or more agents for an interval of time for a skill, requesting an uptime display for an unscheduled time period of the at least one currently unscheduled agent, assessing the type and number of skill types of the at least one currently unscheduled agent, determining a manpower availability for the an interval of time based upon all agents currently scheduled for each skill type based upon the forecasted manpower requirement, calculating a manpower delta between the forecasted manpower requirement for the an interval of time and the determined manpower availability for each skill type, and offering an uptime adjustment if the calculated manpower delta shows additional manpower is required for any skill possessed by the at least one currently unscheduled agent.

Abstract translation: 一种系统，方法和计算机可读介质，用于为具有至少一种技能类型的至少一个当前非调度代理提供对工作进度的正常运行时间调整，其包括：接收零个或多个代理的至少一个预测人力需求， 技能的时间，请求对至少一个当前非调度代理的非预定时间段的正常运行时间显示，评估至少一个当前非调度代理的技能类型的类型和数量，确定一段时间的人力可用性 基于目前根据预测的人力需求计划的每个技能类型的所有代理人，计算一段时间内预测的人力需求与确定的每种技能类型的人力可用性之间的人力三角洲，并且如果计算出的 人力三角洲显示至少一个c拥有的任何技能需要额外的人力 非常不定期的代理

公开(公告)号：US6026461A

公开(公告)日：2000-02-15

申请号：US208139

申请日：1998-12-09

Applicant: William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

Inventor： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC: G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F13/14

CPC classification number: G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Abstract translation: 基于硬件体系结构的非常快速，高效，高度可扩展，高效率的CCNUMA处理系统，可最大限度地减少系统总线争用，通过维护强大的排序和避免重试来最大化处理进度，并实现全映射目录结构高速缓存一致性协议。 缓存相干非均匀存储器访问（CCNUMA）架构在包括由主板和两个子板组成的多个集成模块的系统中实现。 插入主板的子板每个都包含两个作业处理器（JP），高速缓存和输入/输出（I / O）功能。 直接位于主板上的是两个小型计算机系统接口（SCSI）和一个局域网（LAN）接口形式的附加集成I / O功能。 主板包括主存储器，存储器控制器（MC）和用于高速缓存一致性的目录DRAM。 主板还包括GTL背板接口逻辑，系统时钟生成和分配逻辑，以及包括用于系统初始化的微控制器的本地资源。 交叉开关将各种逻辑块连接在一起。 一个完整的主板包含2个JP子板，2个PCI扩展板和最多512 MB的主内存。 每个子板包含两个50MHz的Motorola 88110 JP复合体，具有相关联的88410缓存控制器和1MB 2级缓存。 还提供单个16 MB的第三级直写缓存，并由第三级缓存控制器控制。

公开(公告)号：US20130001355A1

公开(公告)日：2013-01-03

申请号：US13410120

申请日：2012-03-01

Applicant: Isaiah W. Cox ,  Joseph Cox

Inventor： Isaiah W. Cox ,  Joseph Cox

IPC: B64C25/36

CPC classification number: B64C25/405 ,  Y02T50/823

Abstract: A method for reducing the amount of fuel required to be carried in flight by an aircraft is provided that substantially reduces the taxi margin amount of fuel required by an aircraft, thereby reducing the aircraft's weight and producing significant increases in fuel use efficiency and savings in fuel costs. The substantially reduced taxi margin amount of fuel is produced by equipping an aircraft with at least one drive wheel powered by at least one onboard drive means that cooperatively drive the aircraft on the ground during taxi between takeoff and landing without reliance on the operation of the aircraft main engines.

Abstract translation: 提供了一种减少航空器在飞行中携带的燃料量的方法，其大大减少了飞机所需的出租车边际量，从而降低了飞行器的重量并显着增加了燃料使用效率并节省了燃料 费用 大大减少的出租车边际量的燃料是通过为飞机装备至少一个由至少一个驱动装置驱动的驱动轮来产生的，所述驱动轮由起飞和着陆之间的出租车期间协调地驱动飞机在地面上，而不依赖飞行器的操作 主机

公开(公告)号：US20070266763A1

公开(公告)日：2007-11-22

申请号：US11419458

申请日：2006-05-19

Applicant: Ron Therrio ,  Jeremy Determan ,  Joseph Cox ,  Matthew Nevitt

Inventor： Ron Therrio ,  Jeremy Determan ,  Joseph Cox ,  Matthew Nevitt

IPC: G01N3/30

CPC classification number: G01N3/56 ,  A43D999/00

Abstract: This invention discloses a footwear testing device that evaluates the durability of footwear to the wear encountered in the sport of skateboarding.

Abstract translation: 本发明公开了一种鞋类测试装置，其评估鞋类对于滑板运动中遇到的磨损的耐久性。

公开(公告)号：US20070241153A1

公开(公告)日：2007-10-18

申请号：US11554182

申请日：2006-10-30

Applicant: David Medina ,  Joseph Cox ,  Carlos Orozco

Inventor： David Medina ,  Joseph Cox ,  Carlos Orozco

IPC: B60R9/06

CPC classification number: B60R3/02 ,  A61G3/061

Abstract: A loading apparatus for allowing wheelchair access to a vehicle is provided. The apparatus attaches to the hitch receiver of the vehicle, such as a van, truck or similar vehicle. The apparatus includes three ramp section hingidly connected such that the apparatus does not obstruct vision through the rear of the vehicle but also provides sufficient ground clearance for operation of the vehicle.

Abstract translation: 提供一种用于允许轮椅进入​​车辆的装载装置。 该装置连接到车辆的搭接接收器，例如货车，卡车或类似车辆。 该装置包括三个斜坡部分，其铰接连接，使得该装置不阻碍通过车辆后部的视觉，而且还为车辆的操作提供足够的离地间隙。

公开(公告)号：US6122756A

公开(公告)日：2000-09-19

申请号：US11721

申请日：1998-02-10

Applicant: William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Micheal Sporer ,  Doug J. Tucker ,  Simon N. Yeung

Inventor： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Micheal Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC: G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F11/00

CPC classification number: G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

Abstract: A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among the plurality of motherboards and a memory controller module for accessing said main memory interfacing to said motherboard communication bus. Each motherboard also includes at least one daughterboard, detachably connected to thereto. The motherboard further includes a backplane diagnostic bus interface mechanism interfacing each of the motherboards to the backplane diagnostic bus; a microcontroller for processing information and providing outputs and a test bus controller mechanism including registers therein. The system further includes a scan chain that electrically interconnects functionalities mounted on each motherboard and each of the at least one daughter board to the test bus controller; and an applications program for execution with said microcontroller. The applications program including instructions and criteria to automatically test the functionalities and electrical connections and interconnections, to automatically determine the presence of one or more faulted components and to automatically functionally remove the faulted component(s) from the computer system. Also featured is a balanced clock tree circuit that automatically and selectively supplies certain clock pulses to the logical flip/flops of an ASIC. The system further includes redundant clock generation and distribution circuitry that automatically fails to the redundant clock circuitry in the event of a failure of the normal clock source.

Abstract translation: PCT No.PCT / US96 / 13742 Sec。 371日期1998年2月10日 102（e）1998年2月10日PCT PCT 1996年8月14日PCT公布。 公开号WO97 / 07457 日期1997年2月27日一种高可用性计算机系统和方法，包括背板，具有至少一个底板通信总线和诊断总线，多个主板，每个与诊断总线接口。 每个主板还包括包括分配在多个母板中的主存储器的存储器系统和用于访问与所述主板通信总线接口的所述主存储器的存储器控​​制器模块。 每个主板还包括至少一个子板，可拆卸地连接到其上。 主板还包括背板诊断总线接口机构，将每个主板接口连接到背板诊断总线; 用于处理信息并提供输出的微控制器和包括其中的寄存器的测试总线控制器机构。 该系统还包括扫描链，其将安装在每个主板上的功能和至少一个子板中的每一个电互连到测试总线控制器; 以及用于与所述微控制器执行的应用程序。 应用程序包括自动测试功能和电气连接和互连的指令和标准，以自动确定一个或多个故障组件的存在并自动从计算机系统功能地移除故障组件。 还有一个平衡时钟树电路，可自动选择性地向ASIC的逻辑触发器提供某些时钟脉冲。 该系统还包括在正常时钟源故障的情况下自动地对冗余时钟电路故障的冗余时钟产生和分配电路。