公开(公告)号：US20070190751A1

公开(公告)日：2007-08-16

申请号：US11725296

申请日：2007-03-19

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： H01L21/326 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A fuse for use in semiconductor devices, semiconductor devices including the fuse, methods of fabricating the fuse, and methods of using the fuse. The fuse includes terminals and a programmable region between the terminals. The programmable region may have less mass than the terminals. The programmable region may include metal silicide, which is rendered discontinuous by agglomeration or melting when a programming current is applied to one of the terminals. Construction of the fuse or features over the fuse may prevent programming of the fuse with a laser.

摘要翻译： 用于半导体器件的保险丝，包括保险丝的半导体器件，制造保险丝的方法以及使用保险丝的方法。 保险丝包括端子和端子之间的可编程区域。 可编程区域的质量可能比端子少。 可编程区域可以包括金属硅化物，当编程电流施加到端子之一时，其通过聚集或熔化而变得不连续。 保险丝或特征超过保险丝的构造可能会导致使用激光对熔丝进行编程。

公开(公告)号：US20060231922A1

公开(公告)日：2006-10-19

申请号：US11426523

申请日：2006-06-26

申请人： Kenneth Marr ,  John Porter

发明人： Kenneth Marr ,  John Porter

IPC分类号： H01L29/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0248 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

摘要翻译： 根据本发明的实施例，电路具有用于保护栅介质反熔丝电路中的高压晶体管的元件。 反熔丝在耦合以接收升高电压的第一端子和第二端子之间具有栅极电介质层，并且高压晶体管耦合到反熔丝并具有栅极端子。 电源电压和升高电压之间的中间电压耦合到高电压晶体管的栅极端子，以保护高压晶体管。

公开(公告)号：US20050158919A1

公开(公告)日：2005-07-21

申请号：US11082066

申请日：2005-03-16

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link joining the spaced-apart terminals and including a single layer of conductive material. A first, lower layer of the terminals of each fuse may be formed from conductively doped polysilicon. The second, upper layer of each fuse terminal may be formed from a polycide, a metal silicide, a metal, or a conductive alloy. The conductive link of each fuse may be formed from either the material of the first layer or the material of the second layer. Methods for fabricating the fuse include forming the first and second layers and patterning the first and second layers so as to form a fuse with the desired structure.

摘要翻译： 用于半导体器件的熔断器包括具有至少两层导电材料的间隔开的端子和连接间隔开的端子并包括单层导电材料的单层导电连接。 每个保险丝的端子的第一个下层可以由导电掺杂的多晶硅形成。 每个熔丝端子的第二上层可以由多晶硅，金属硅化物，金属或导电合金形成。 每个保险丝的导电连接可由第一层的材料或第二层的材料形成。 用于制造熔丝的方法包括形成第一层和第二层并且图案化第一层和第二层以便形成具有所需结构的熔丝。

公开(公告)号：US20050029598A1

公开(公告)日：2005-02-10

申请号：US10931366

申请日：2004-08-31

申请人： Kenneth Marr ,  John Porter

发明人： Kenneth Marr ,  John Porter

IPC分类号： G11C17/18 ,  H01L23/525 ,  H01L29/78 ,  H01L29/04

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0248 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.

公开(公告)号：US20050174138A1

公开(公告)日：2005-08-11

申请号：US11065016

申请日：2005-02-24

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

CPC分类号： G01R31/2856 ,  G01R31/287 ,  G01R31/318505 ,  G01R31/318511 ,  G11C16/04 ,  G11C29/006 ,  G11C29/12 ,  G11C29/44 ,  G11C2029/4402 ,  G11C2029/5002

摘要： A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. Circuits and systems associated with the method of the present invention are also disclosed.

摘要翻译： 公开了一种用于从晶片级老化确定老化可靠性的方法，电路和系统。 根据本发明的方法包括在晶片级老化测试的持续时间内的时间点上将每个IC管芯中的故障数记录在片上的非易失性元件中。 每个IC芯片中的故障数量及其相关联的时间点可用于创建老化可靠性曲线，其通常使用其他可能具有较低成本效益或不可能通过未封装的IC芯片实现的其他过程得到。 还公开了与本发明的方法相关的电路和系统。

公开(公告)号：US20050018499A1

公开(公告)日：2005-01-27

申请号：US10925543

申请日：2004-08-24

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/12 ,  G11C29/44

CPC分类号： G01R31/2856 ,  G01R31/287 ,  G01R31/318505 ,  G01R31/318511 ,  G11C16/04 ,  G11C29/006 ,  G11C29/12 ,  G11C29/44 ,  G11C2029/4402 ,  G11C2029/5002

摘要： An apparatus for determining burn-in reliability from wafer level burn-in is disclosed. The apparatus according td the present invention includes nonvolatile elements on an integrated circuit for recording the number of failures at various points in time over the duration of wafer level burn-in testing. The number of failures in each IC die, along with their associated points in time, may be used to create burn-in reliability curves which are conventionally derived using other processes that may be less cost effective or not possible to effect with unpackaged IC dice. A memory device associated with the method of the present invention is also disclosed.

摘要翻译： 公开了一种用于从晶片级老化确定老化可靠性的装置。 根据本发明的装置包括用于在晶片级老化测试的持续时间内记录不同时间点的故障次数的集成电路上的非易失性元件。 每个IC芯片中的故障数量及其相关联的时间点可用于创建老化可靠性曲线，其通常使用其他可能具有较低成本效益或不可能通过未封装的IC芯片实现的其他过程得到。 还公开了与本发明的方法相关联的存储器件。

公开(公告)号：US20050015654A1

公开(公告)日：2005-01-20

申请号：US10609312

申请日：2003-06-24

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G11C29/00 ,  H02H3/05

CPC分类号： G11C29/832 ,  G11C29/83

摘要： A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the supply control circuit isolates the defective memory segment from the supply source. The memory device replaces the defective memory segment with a redundant segment.

摘要翻译： 存储器件具有通过电源控制电路连接到电源的多个存储器段。 如果其中一个存储器段有故障，则电源控制电路将有缺陷的存储器段与供电源隔离。 存储器件用冗余段替换有缺陷的存储器段。

公开(公告)号：US20110140227A1

公开(公告)日：2011-06-16

申请号：US12653437

申请日：2009-12-14

申请人： Michael A. Smith ,  Vladimir Mikhalev ,  Kenneth Marr ,  Haitao Liu

发明人： Michael A. Smith ,  Vladimir Mikhalev ,  Kenneth Marr ,  Haitao Liu

IPC分类号： H01L29/06

CPC分类号： H01L27/11526 ,  H01L27/0266 ,  H01L27/11529

摘要： A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.

摘要翻译： 一种非易失性微电子存储器件，其包括耗尽模式电路保护装置，其防止在擦除操作期间施加到位线的高电压被施加到和电连接到位线的低电压电路。

公开(公告)号：US20070168772A1

公开(公告)日：2007-07-19

申请号：US11492254

申请日：2006-07-25

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G11C29/00

CPC分类号： G11C29/832 ,  G11C29/83

摘要： Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory segment is defective. The memory device replaces a defective memory segment with a redundant segment. Other embodiments are described and claimed.

公开(公告)号：US20070168771A1

公开(公告)日：2007-07-19

申请号：US11492250

申请日：2006-07-25

申请人： Kenneth Marr

发明人： Kenneth Marr

IPC分类号： G11C29/00

CPC分类号： G11C29/832 ,  G11C29/83

摘要： Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory segment is defective. The memory device replaces a defective memory segment with a redundant segment. Other embodiments are described and claimed.

摘要翻译： 本发明的一些实施例包括存储器件，其具有通过电源控制电路连接到电源的多个存储器段。 当选择的存储器段有缺陷时，电源控制电路将所选择的存储器段与电源相隔离。 存储器件用冗余段替换有缺陷的存储器段。 描述和要求保护其他实施例。