公开(公告)号：US4279012A

公开(公告)日：1981-07-14

申请号：US953558

申请日：1978-10-23

Applicant: David L. Beckedorff ,  Michael Sporer ,  Bruce R. Watts

Inventor： David L. Beckedorff ,  Michael Sporer ,  Bruce R. Watts

IPC: G05B19/10 ,  G06F17/00 ,  H04Q9/00 ,  G06F15/20 ,  H01H43/00

CPC classification number: G05B19/102 ,  Y10T307/957

Abstract: Programmable apparatus for providing random on/off control of electrical devices such as appliances. Such control may be programmed for an entire week, with different programming for each day, and with programming control over small blocks of time, e.g. thirty minutes. Programming is secured by the use of a combination or lock and, in addition, the AC line cord of the electrical device, which receives or does not receive AC power depending upon the status of the program, is locked into the apparatus. During operation, the program in the apparatus may be interrogated and displayed; otherwise the time of day is displayed. The apparatus also includes a look-ahead feature, turning on an appliance, such as a television set, earlier than programmed in order to provide sufficient warm-up time.

Abstract translation: 用于提供诸如电器的电气设备的随机开/关控制的可编程设备。 这样的控制可以被编程整整一个星期，每天都有不同的编程，以及对小时间段的编程控制，例如， 三十分钟。 通过使用组合或锁定来保护编程，并且另外根据程序的状态接收或不接收AC电力的电气设备的交流电源线被锁定到设备中。 在操作期间，可以询问并显示设备中的程序; 否则显示时间。 该装置还包括一个预先的功能，其比早于编程的开启诸如电视机之类的设备，以便提供足够的预热时间。

公开(公告)号：US09195695B2

公开(公告)日：2015-11-24

申请号：US11900931

申请日：2007-09-13

Applicant: John Yates ,  Michael Sporer ,  Sharon Miller

Inventor： John Yates ,  Michael Sporer ,  Sharon Miller

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30321 ,  G06F17/30153 ,  G06F17/30371

Abstract: An approach for providing compression of a database table that uses a compiled table algorithm (CTA) that provides leverage. Data within any given column in adjacent rows is often the same as or closely related to its neighbors. Rather than storing data in each column of each row as a specific integer, floating point, or character data value, a field reconstruction instruction is stored that when executed by a decompression engine can reconstruct the data value. The field reconstruction instruction may be bit granular and may depend upon past history given that the data compression engine may preserve state as row data is streamed off a storage device.

Abstract translation: 提供使用提供杠杆的编译表算法（CTA）的数据库表的压缩的方法。 相邻行中任何给定列中的数据通常与其邻居相同或密切相关。 不是将每行的每列中的数据存储为特定整数，浮点或字符数据值，而是存储一个字段重构指令，当被解压缩引擎执行时可以重构数据值。 场重建指令可以是位细粒度的，并且可以依赖于过去的历史，因为数据压缩引擎可以在行数据从存储设备流传输时保留状态。

公开(公告)号：US06584152B2

公开(公告)日：2003-06-24

申请号：US09734276

申请日：2000-12-11

Applicant: Michael Sporer ,  Katherine H. Cornog ,  Peter Zawojski ,  James Hamilton

Inventor： Michael Sporer ,  Katherine H. Cornog ,  Peter Zawojski ,  James Hamilton

IPC: H04B166

CPC classification number: H05K1/0216 ,  G06T9/004 ,  G11B27/034 ,  G11B27/105 ,  G11B33/08 ,  G11B33/12 ,  G11B33/144 ,  G11B2220/20 ,  H05K2201/09236 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed, by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Abstract translation: 通过在每个帧内压缩图像之前将状态信息添加到比特流来增强对使用帧间和帧内技术压缩的视频片段的任意字段的随机访问，以通过生成映射每个帧内压缩图像的场索引来允许每个帧内压缩图像被随机访问 时间字段到用于解码字段的数据的压缩比特流中的偏移量，以及通过使用两个或更多个交替使用的解码器来播放段。 可以通过从应用于每个解码器的比特流中消除与双向压缩图像相对应的任何数据来改进切割密度，否则解码器将使用该数据来在所需字段之前生成字段。

公开(公告)号：US6026461A

公开(公告)日：2000-02-15

申请号：US208139

申请日：1998-12-09

Applicant: William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

Inventor： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC: G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F13/14

CPC classification number: G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Abstract translation: 基于硬件体系结构的非常快速，高效，高度可扩展，高效率的CCNUMA处理系统，可最大限度地减少系统总线争用，通过维护强大的排序和避免重试来最大化处理进度，并实现全映射目录结构高速缓存一致性协议。 缓存相干非均匀存储器访问（CCNUMA）架构在包括由主板和两个子板组成的多个集成模块的系统中实现。 插入主板的子板每个都包含两个作业处理器（JP），高速缓存和输入/输出（I / O）功能。 直接位于主板上的是两个小型计算机系统接口（SCSI）和一个局域网（LAN）接口形式的附加集成I / O功能。 主板包括主存储器，存储器控制器（MC）和用于高速缓存一致性的目录DRAM。 主板还包括GTL背板接口逻辑，系统时钟生成和分配逻辑，以及包括用于系统初始化的微控制器的本地资源。 交叉开关将各种逻辑块连接在一起。 一个完整的主板包含2个JP子板，2个PCI扩展板和最多512 MB的主内存。 每个子板包含两个50MHz的Motorola 88110 JP复合体，具有相关联的88410缓存控制器和1MB 2级缓存。 还提供单个16 MB的第三级直写缓存，并由第三级缓存控制器控制。

公开(公告)号：US5883670A

公开(公告)日：1999-03-16

申请号：US691985

申请日：1996-08-02

Applicant: Michael Sporer ,  Mark H. Kline ,  Peter Zawojski

Inventor： Michael Sporer ,  Mark H. Kline ,  Peter Zawojski

IPC: G06F3/033 ,  G06F3/048 ,  G06T3/40 ,  G11B27/032 ,  G11B27/034 ,  G11B27/34 ,  G11B27/36 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12 ,  H04N9/475 ,  H04N11/02 ,  H04N11/04

CPC classification number: H04N19/00 ,  G06F3/0483 ,  G06T3/4023 ,  G11B27/034 ,  G11B27/34 ,  H04N19/40 ,  H04N19/42 ,  H04N19/61 ,  H04N19/85 ,  H04N21/4143 ,  G11B2220/213 ,  G11B2220/2512 ,  G11B2220/2545 ,  G11B2220/41 ,  G11B2220/90 ,  G11B27/032 ,  G11B27/36

Abstract: A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format. By having processors for handling two compression formats for motion video data connected to this data path, conversion between compression formats, such as between MPEG to Motion JPEG, can be performed.

Abstract translation: 数字运动视频处理电路可以使用计算机的系统存储器捕获，回放和操纵数字运动视频信息，作为用于保存来自电路的压缩视频数据的数据缓冲器。 系统存储器可以由标准总线上的电路访问。 电路中的控制器在传送像素数据流的输入/输出端口与标准总线之间引导数据流。 控制器通过用于压缩，解压缩，缩放和缓冲的处理电路将数据传送到标准总线或输入/输出端口。 标准总线可以是外围组件互连（PCI）总线。 运动视频处理电路具有包括像素数据和指示由像素数据定义的图像的大小的定时数据的数据路径。 定时数据由处理像素数据的每个组件使用和/或生成，从而使得每个组件能够在没有图像格式的知识的情况下处理像素数据。 通过具有用于处理连接到该数据路径的运动视频数据的两种压缩格式的处理器，可以执行诸如MPEG到Motion JPEG之间的压缩格式之间的转换。

公开(公告)号：US07730077B2

公开(公告)日：2010-06-01

申请号：US10667203

申请日：2003-09-18

Applicant: Foster D. Hinshaw ,  Raymond J. Andraka ,  David L. Meyers ,  Sharon L. Miller ,  Michael Sporer ,  William K. Stewart ,  Barry M. Zane

Inventor： Foster D. Hinshaw ,  Raymond J. Andraka ,  David L. Meyers ,  Sharon L. Miller ,  Michael Sporer ,  William K. Stewart ,  Barry M. Zane

IPC: G06F17/30

CPC classification number: G06F17/30477 ,  G06F17/30578 ,  Y10S707/99944

Abstract: A programmable streaming data processor that can be programmed to recognize record and field structures of data received from a streaming data source such as a mass storage device. Being programmed with, for example, field information, the unit can locate record and field boundaries and employ logical arithmetic methods to compare fields with one another or with values otherwise supplied by general purpose processors to precisely determine which records are worth transferring to memory of the more general purpose distributed processors. The remaining records arrive and are discarded by the streaming data processor or are tagged with status bits to indicate to the more general purpose processor that they are to be ignored. In a preferred embodiment, the streaming data processor may analyze and discard records for several reasons. The first reason may be an analysis of contents of the field. Other reasons for record blocking may have to do with tagging records that are to be visible to particular users depending upon a series of concurrent transactions.

Abstract translation: 可编程流式数据处理器，其可以被编程以识别从诸如大容量存储设备的流数据源接收的数据的记录和场结构。 通过例如场信息进行编程，该单元可以定位记录和场边界，并采用逻辑运算方法将场相互比较，或者由通用处理器提供的值精确地确定哪些记录值得转移到 更通用的分布式处理器。 剩余的记录到达并被流式数据处理器丢弃，或者被标记为状态位，以向更通用的处理器指示它们被忽略。 在优选实施例中，流数据处理器可以由于几个原因来分析和丢弃记录。 第一个原因可能是对该领域内容的分析。 记录阻止的其他原因可能与标记根据一系列并发事务对特定用户可见的记录有关。

公开(公告)号：US20080222136A1

公开(公告)日：2008-09-11

申请号：US11900931

申请日：2007-09-13

Applicant: John Yates ,  Michael Sporer ,  Sharon Miller

Inventor： John Yates ,  Michael Sporer ,  Sharon Miller

IPC: G06F17/30 ,  G06F7/06

CPC classification number: G06F17/30321 ,  G06F17/30153 ,  G06F17/30371

Abstract: An approach for providing compression of a database table that uses a compiled table algorithm (CTA) that provides leverage. Data within any given column in adjacent rows is often the same as or closely related to its neighbors. Rather than storing data in each column of each row as a specific integer, floating point, or character data value, a field reconstruction instruction is stored that when executed by a decompression engine can reconstruct the data value. The field reconstruction instruction may be bit granular and may depend upon past history given that the data compression engine may preserve state as row data is streamed off a storage device.

Abstract translation: 提供使用提供杠杆的编译表算法（CTA）的数据库表的压缩的方法。 相邻行中任何给定列中的数据通常与其邻居相同或密切相关。 不是将每行的每列中的数据存储为特定整数，浮点或字符数据值，而是存储一个字段重构指令，当被解压缩引擎执行时可以重构数据值。 场重建指令可以是位细粒度的，并且可以依赖于过去的历史，因为数据压缩引擎可以在行数据从存储设备流传输时保留状态。

公开(公告)号：US6167083A

公开(公告)日：2000-12-26

申请号：US832987

申请日：1997-04-04

Applicant: Michael Sporer ,  Katherine H. Cornog ,  Peter Zawojski ,  James Hamilton

Inventor： Michael Sporer ,  Katherine H. Cornog ,  Peter Zawojski ,  James Hamilton

IPC: H04N5/92 ,  G06T9/00 ,  G11B27/034 ,  G11B27/10 ,  G11B33/08 ,  G11B33/12 ,  G11B33/14 ,  H04N5/91 ,  H04N7/32 ,  H05K1/02 ,  H04B1/66

CPC classification number: H05K1/0216 ,  G06T9/004 ,  G11B27/034 ,  G11B27/105 ,  G11B33/08 ,  G11B33/12 ,  G11B33/144 ,  G11B2220/20 ,  H05K2201/09236 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: Random access to arbitrary fields of a video segment compressed using both interframe and intraframe techniques is enhanced by adding state information to the bitstream prior to each intraframe compressed image to allow each intraframe compressed image to be randomly accessed by generating a field index that maps each temporal field to the offset in the compressed bitstream of the data used to decode the field, and by playing back segments using two or more alternatingly used decoders. The cut density may be improved by eliminating from the bitstream applied to each decoder any data corresponding to bidirectionally compressed images that would otherwise be used by the decoder to generate fields prior to the desired field.

Abstract translation: 通过在每个帧内压缩图像之前将状态信息添加到比特流来增强对使用帧间和帧内技术压缩的视频片段的任意字段的随机访问，以允许每个帧内压缩图像通过生成映射每个时间间隔的场索引来随机访问 字段到用于解码字段的数据的压缩比特流中的偏移量，以及通过使用两个或更多个交替使用的解码器回放段。 可以通过从应用于每个解码器的比特流中消除与双向压缩图像相对应的任何数据来改进切割密度，否则解码器将使用该数据来在所需字段之前生成字段。

公开(公告)号：US6091778A

公开(公告)日：2000-07-18

申请号：US211057

申请日：1998-12-14

Applicant: Michael Sporer ,  Mark H. Kline ,  Peter Zawojski

Inventor： Michael Sporer ,  Mark H. Kline ,  Peter Zawojski

IPC: G06F3/033 ,  G06F3/048 ,  G06T3/40 ,  G11B27/032 ,  G11B27/034 ,  G11B27/34 ,  G11B27/36 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12

CPC classification number: H04N19/00 ,  G06F3/0483 ,  G06T3/4023 ,  G11B27/034 ,  G11B27/34 ,  H04N19/40 ,  H04N19/42 ,  H04N19/61 ,  H04N19/85 ,  H04N21/4143 ,  G11B2220/213 ,  G11B2220/2512 ,  G11B2220/2545 ,  G11B2220/41 ,  G11B2220/90 ,  G11B27/032 ,  G11B27/36

Abstract: A digital motion video processing circuit can capture, playback and manipulate digital motion video information using the system memory of a computer as a data buffer for holding compressed video data from the circuit. The system memory may be accessed by the circuit over a standard bus. A controller in the circuit directs data flow between an input/output port which transfer a stream of pixel data and to the standard bus. The controller directs data to and from either the standard bus or the input/output port through processing circuitry for compression, decompression, scaling and buffering. The standard bus may be a peripheral component interconnect (PCI) bus. The motion video processing circuit has a data path including pixel data and timing data indicative of a size of an image defined by the pixel data. The timing data is used and/or generated by each component which processes the pixel data, thereby enabling each component to process the pixel data without prior knowledge of the image format. By having processors for handling two compression formats for motion video data connected to this data path, conversion between compression formats, such as between MPEG to Motion JPEG, can be performed.

Abstract translation: 数字运动视频处理电路可以使用计算机的系统存储器捕获，回放和操纵数字运动视频信息，作为用于保存来自电路的压缩视频数据的数据缓冲器。 系统存储器可以由标准总线上的电路访问。 电路中的控制器在传送像素数据流的输入/输出端口与标准总线之间引导数据流。 控制器通过用于压缩，解压缩，缩放和缓冲的处理电路将数据传送到标准总线或输入/输出端口。 标准总线可以是外围组件互连（PCI）总线。 运动视频处理电路具有包括像素数据和指示由像素数据定义的图像的大小的定时数据的数据路径。 定时数据由处理像素数据的每个组件使用和/或生成，从而使得每个组件能够在没有图像格式的知识的情况下处理像素数据。 通过具有用于处理连接到该数据路径的运动视频数据的两种压缩格式的处理器，可以执行诸如MPEG到Motion JPEG之间的压缩格式之间的转换。

公开(公告)号：US5887146A

公开(公告)日：1999-03-23

申请号：US695556

申请日：1996-08-12

Applicant: William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

Inventor： William F. Baxter ,  Robert G. Gelinas ,  James M. Guyer ,  Dan R. Huck ,  Michael F. Hunt ,  David L. Keating ,  Jeff S. Kimmell ,  Phil J. Roux ,  Liz M. Truebenbach ,  Rob P. Valentine ,  Pat J. Weiler ,  Joseph Cox ,  Barry E. Gillott ,  Andrea Heyda ,  Rob J. Pike ,  Tom V. Radogna ,  Art A. Sherman ,  Michael Sporer ,  Doug J. Tucker ,  Simon N. Yeung

IPC: G06F11/20 ,  G06F1/04 ,  G06F11/22 ,  G06F11/267 ,  G06F12/08 ,  G06F13/36 ,  G06F13/00 ,  G06F1/12

CPC classification number: G06F11/2289 ,  G06F11/22 ,  G06F11/267 ,  G06F12/0813 ,  G06F13/36 ,  G06F2212/2542

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency. The motherboard also includes GTL backpanel interface logic, system clock generation and distribution logic, and local resources including a micro-controller for system initialization. A crossbar switch connects the various logic blocks together. A fully loaded motherboard contains 2 JP daughterboards, two PCI expansion boards, and up to 512 MB of main memory. Each daughterboard contains two 50 MHz Motorola 88110 JP complexes, having an associated 88410 cache controller and 1 MB Level 2 Cache. A single 16 MB third level write-through cache is also provided and is controlled by a third level cache controller.

Abstract translation: 基于硬件体系结构的非常快速，高效，高度可扩展，高效率的CCNUMA处理系统，可最大限度地减少系统总线争用，通过维护强大的排序和避免重试来最大化处理进度，并实现全映射目录结构高速缓存一致性协议。 缓存相干非均匀存储器访问（CCNUMA）架构在包括由主板和两个子板组成的多个集成模块的系统中实现。 插入主板的子板每个都包含两个作业处理器（JP），高速缓存和输入/输出（I / O）功能。 直接位于主板上的是两个小型计算机系统接口（SCSI）和一个局域网（LAN）接口形式的附加集成I / O功能。 主板包括主存储器，存储器控制器（MC）和用于高速缓存一致性的目录DRAM。 主板还包括GTL背板接口逻辑，系统时钟生成和分配逻辑，以及包括用于系统初始化的微控制器的本地资源。 交叉开关将各种逻辑块连接在一起。 一个完整的主板包含2个JP子板，2个PCI扩展板和最多512 MB的主内存。 每个子板包含两个50MHz的Motorola 88110 JP复合体，具有相关联的88410缓存控制器和1MB 2级缓存。 还提供单个16 MB的第三级直写缓存，并由第三级缓存控制器控制。