公开(公告)号：US11226902B2

公开(公告)日：2022-01-18

申请号：US16588380

申请日：2019-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Benjamin Herrenschmidt ,  Cathy May ,  Bradly G. Frey

IPC: G06F12/1009 ,  G06F12/1027

Abstract: A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

公开(公告)号：US10817434B2

公开(公告)日：2020-10-27

申请号：US16225803

申请日：2018-12-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Benjamin Herrenschmidt ,  Cathy May ,  Bradly G. Frey

IPC: G06F12/1027 ,  G06F12/0815 ,  G06F9/52 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F12/0842

Abstract: A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread, a synchronization instruction following the translation invalidation instruction in program order that determines completion of invalidation, at all of the plurality of processor cores, of the translation entries specified by the translation invalidation instruction and draining of any memory referent instructions whose target addresses have been translated by reference to the translation entries. A register is updated to a state based on a result of the determination. The processor core branches execution to re-execute the synchronization instruction based on the state of the register indicating that the translation entries are not invalidated at all of the plurality of processor cores.

公开(公告)号：US10387686B2

公开(公告)日：2019-08-20

申请号：US15661048

申请日：2017-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard H. Boivie ,  Bradly G. Frey ,  William E. Hall ,  Benjamin Herrenschmidt ,  Guerney D. H. Hunt ,  Jentje Leenstra ,  Paul Mackerras ,  Cathy May ,  Albert J. Van Norstrand, Jr.

IPC: G06F9/46 ,  G06F21/74 ,  G06F9/455 ,  G06F21/53

Abstract: Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.

公开(公告)号：US10152322B2

公开(公告)日：2018-12-11

申请号：US15243413

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bradly G. Frey ,  Sanjeev Ghai ,  Guy L. Guthrie ,  Cathy May ,  William J. Starke ,  Derek E. Williams

IPC: G06F9/30 ,  G06F12/0811 ,  G06F12/0879 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/0831

Abstract: A processor core has a store-through upper level cache and a store-in lower level cache. In response to execution of a memory move instruction sequence including a plurality of copy-type instruction and a plurality of paste-type instructions, the processor core transmits a corresponding plurality of copy-type and paste-type requests to the lower level cache, where each copy-type request specifies a source real address and each paste-type request specifies a destination real address. In response to receipt of each copy-type request, the lower level cache copies a respective one of a plurality of data granules from a respective storage location specified by the source real address of that copy-type request into a non-architected buffer. In response to receipt of each paste-type request, the lower level cache writes a respective one of the plurality of data granules from the non-architected buffer to a respective storage location specified by the destination real address of that paste-type request.

公开(公告)号：US09785557B1

公开(公告)日：2017-10-10

申请号：US15333833

申请日：2016-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bradly G. Frey ,  Guy L. Guthrie ,  Cathy May ,  Derek E. Williams

IPC: G06F12/00 ,  G06F12/0837 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/12

CPC classification number: G06F12/0837 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/6042 ,  G06F2212/682 ,  G06F2212/683

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.

公开(公告)号：US09772945B1

公开(公告)日：2017-09-26

申请号：US15333873

申请日：2016-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bradly G. Frey ,  Guy L. Guthrie ,  Cathy May ,  Derek E. Williams

IPC: G06F12/00 ,  G06F12/0837 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/12

CPC classification number: G06F12/0837 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/6042 ,  G06F2212/682 ,  G06F2212/683

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address. Subsequent memory referent instructions can be ordered with respect to the broadcast synchronization request by a synchronization instruction.

公开(公告)号：US20140101359A1

公开(公告)日：2014-04-10

申请号：US13646770

申请日：2012-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Bybell ,  David D. Dukro ,  Bradly G. Frey ,  Michael K. Gschwind

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/1036 ,  G06F2212/151

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract translation: 提供了一种地址转换能力，其中使用不同类型的翻译结构将存储器地址从一种格式转换为另一格式。 在系统配置中同时支持多种翻译结构格式（例如，多页表格式，例如散列页表和分层页表）。 这有助于在虚拟操作系统中提供访客访问，和/或翻译格式的混合以更好地匹配被翻译的数据访问模式。

公开(公告)号：US20190034666A1

公开(公告)日：2019-01-31

申请号：US15661048

申请日：2017-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard H. Boivie ,  Bradly G. Frey ,  William E. Hall ,  Benjamin Herrenschmidt ,  Guerney D. H. Hunt ,  Jentje Leenstra ,  Paul Mackerras ,  Cathy May ,  Albert J. Van Norstrand, JR.

IPC: G06F21/74 ,  G06F9/455 ,  G06F21/53

CPC classification number: G06F21/74 ,  G06F9/45558 ,  G06F21/53 ,  G06F2009/45587 ,  G06F2221/2143 ,  G06F2221/2149

Abstract: Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.

公开(公告)号：US09747212B2

公开(公告)日：2017-08-29

申请号：US13835510

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Wen-Tzer Thomas Chen, Jr. ,  Robert H. Bell, Jr. ,  Bradly G. Frey

IPC: G06F12/0846

CPC classification number: G06F12/0848

Abstract: Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.

公开(公告)号：US09367263B2

公开(公告)日：2016-06-14

申请号：US13657012

申请日：2012-10-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bradly G. Frey ,  Guy L. Guthrie ,  Cathy May ,  Derek E. Williams

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F3/0668 ,  G06F9/467 ,  G06F12/0811

Abstract: A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction.

Abstract translation: 具有共享存储器系统的数据处理系统的处理单元执行包括事务存储指令的存储器事务处理，该指令使得数据处理系统的处理单元对共享存储器系统的目标存储器块进行条件更新 承诺内存交易。 存储器事务还包括事务检查指令。 响应于执行交易检查指令，处理单元在结束存储器事务之前确定在由事务存储指令的执行引起的条件更新之后是否修改了共享存储器系统的目标存储器块。 响应于确定目标存储器块已被修改，处理单元内的条件寄存器被设置为指示存储器事务的冲突。