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公开(公告)号：US20240196766A1
公开(公告)日：2024-06-13
申请号：US18063189
申请日：2022-12-08
发明人： Matthew Joseph BrightSky , Cheng-Wei Cheng , Guy M. Cohen , Robert L. Bruce , Asit Ray , Wanki Kim
IPC分类号： H01L47/00
CPC分类号： H01L45/1246 , H01L45/06 , H01L45/144
摘要： An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.
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公开(公告)号：US10833268B2
公开(公告)日：2020-11-10
申请号：US16287485
申请日：2019-02-27
发明人： Hiroyuki Miyazoe , Takashi Ando , Asit Ray , Seyoung Kim
摘要： Devices and/or methods that facilitate forming a resistive memory crossbar array with a multilayer hardmask are provided. In some embodiments, a resistive random access memory (RRAM) can comprise a multilayer hardmask comprising three layers, an interlayer oxide between a first layer of silicon nitride and a second layer of silicon nitride. In other embodiments, an RRAM can comprise a multilayer hardmask comprising two layers, a layer of an oxide on a layer of silicon nitride.
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公开(公告)号：US20210050384A1
公开(公告)日：2021-02-18
申请号：US16542929
申请日：2019-08-16
IPC分类号： H01L27/24 , H01L45/00 , H01L29/04 , H01L29/16 , H01L29/861 , H01L29/66 , H01L21/02 , H01L21/306 , H01L21/3213
摘要： A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.
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公开(公告)号：US20200274061A1
公开(公告)日：2020-08-27
申请号：US16286912
申请日：2019-02-27
发明人： Hiroyuki Miyazoe , Seyoung Kim , Asit Ray , Takashi Ando
IPC分类号： H01L45/00
摘要： Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.
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公开(公告)号：US20230301217A1
公开(公告)日：2023-09-21
申请号：US18321914
申请日：2023-05-23
发明人： Hiroyuki Miyazoe , Seyoung Kim , Asit Ray , Takashi Ando
IPC分类号： H10N70/00
CPC分类号： H10N70/841 , H10N70/021 , H10N70/8833
摘要： Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.
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公开(公告)号：US20200274067A1
公开(公告)日：2020-08-27
申请号：US16287485
申请日：2019-02-27
发明人： Hiroyuki Miyazoe , Takashi Ando , Asit Ray , Seyoung Kim
摘要： Devices and/or methods that facilitate forming a resistive memory crossbar array with a multilayer hardmask are provided. In some embodiments, a resistive random access memory (RRAM) can comprise a multilayer hardmask comprising three layers, an interlayer oxide between a first layer of silicon nitride and a second layer of silicon nitride. In other embodiments, an RRAM can comprise a multilayer hardmask comprising two layers, a layer of an oxide on a layer of silicon nitride.
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公开(公告)号：US11730070B2
公开(公告)日：2023-08-15
申请号：US16286912
申请日：2019-02-27
发明人： Hiroyuki Miyazoe , Seyoung Kim , Asit Ray , Takashi Ando
IPC分类号： H10N70/00
CPC分类号： H10N70/841 , H10N70/021 , H10N70/8833
摘要： Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.
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公开(公告)号：US10971546B2
公开(公告)日：2021-04-06
申请号：US16542929
申请日：2019-08-16
IPC分类号： H01L27/24 , H01L21/3213 , H01L45/00 , H01L29/04 , H01L29/16 , H01L29/861 , H01L29/66 , H01L21/02 , H01L21/306
摘要： A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.
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