公开(公告)号：US20240312819A1

公开(公告)日：2024-09-19

申请号：US18185427

申请日：2023-03-17

Applicant: Intel Corporation

Inventor： Hong Seung YEON ,  Mariano PHIELIPP ,  Yi LI ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN

IPC: H01L21/68 ,  H01L21/67

CPC classification number: H01L21/68 ,  H01L21/67259

Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.

公开(公告)号：US20230300063A1

公开(公告)日：2023-09-21

申请号：US18200342

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： Helia A. NAEIMI ,  Amedeo SAPIO ,  John Andrew FINGERHUT ,  Yi LI ,  Yanfang LE

IPC: H04L45/16 ,  H04L69/22

CPC classification number: H04L45/16 ,  H04L69/22

Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: receive a first packet comprising a first packet header and a first packet payload; receive multiple subsequent packets comprising multiple packet headers for respective multiple subsequent packets; update at least one of the multiple packet headers; and construct egress packets. In some examples, the egress packets include respective one of the multiple packet headers and the first packet payload.

公开(公告)号：US20240078702A1

公开(公告)日：2024-03-07

申请号：US17902907

申请日：2022-09-05

Applicant: Intel Corporation

Inventor： Yi LI ,  Hong Seung YEON ,  Nicholas HAEHN ,  Wei LI ,  Raquel DE SOUZA BORGES FERREIRA ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN ,  Arnab ROY

IPC: G06T7/73 ,  H01L21/68 ,  H01L23/544

CPC classification number: G06T7/74 ,  H01L21/681 ,  H01L23/544 ,  G06T2207/20081 ,  G06T2207/30204 ,  H01L2223/54426

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

公开(公告)号：US20230239196A1

公开(公告)日：2023-07-27

申请号：US18130383

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Junggun LEE ,  Anurag AGRAWAL ,  Yi LI ,  Jeremias BLENDIN ,  Yanfang LE

IPC: H04L41/0681 ,  H04L69/22 ,  H04L47/11

CPC classification number: H04L41/0681 ,  H04L47/115 ,  H04L69/22

Abstract: An apparatus is described. The apparatus includes electronic circuitry to support multiple flows within a network. The electronic circuitry to determine respective telemetry information for the multiple flows and inject an alarm message into a particular one of the multiple flows upon an alarm condition being reached for the particular one flow. The alarm message includes a multi-bit error code that describes the alarm condition. The multi-bit error code is one of multiple, possible multi-bit error codes.

公开(公告)号：US20220078119A1

公开(公告)日：2022-03-10

申请号：US17475203

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Prateesh GOYAL ,  Georgios NIKOLAIDIS ,  Junggun LEE ,  Jeremias BLENDIN ,  Yi LI

IPC: H04L12/803

Abstract: Examples described herein relate to a network interface device that includes data plane circuitry, when operational, to: identify a flow of packets that is a cause of queue congestion and cause transmission, to an upstream network interface device, of a packet with an identifier of a source queue in the upstream network interface device that requests reduction of transmission of packets from the source queue associated with the upstream network interface device. In some examples, the source queue is identified in a congestion causing packet by the upstream network interface device and wherein the upstream network interface device comprises a prior hop network interface device.

公开(公告)号：US20250144857A1

公开(公告)日：2025-05-08

申请号：US18500132

申请日：2023-11-02

Applicant: Intel Corporation

Inventor： Zhixin XIE ,  Yi LI ,  Jesse JONES ,  Gang DUAN ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Yekan WANG

IPC: B29C45/14 ,  B29C45/26

Abstract: Various aspects may provide a molding system. The molding system may include a molding unit which includes a first mold panel and a second mold panel. The first mold panel and the second mold panel may include a mold cavity which surrounds a semiconductor workpiece along a side surface of the semiconductor workpiece, with the first mold panel and the second mold panel engaged with the semiconductor workpiece. Various aspects may also provide a molding method which utilize the molding system.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20230033086A1

公开(公告)日：2023-02-02

申请号：US17791175

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Chen WANG ,  Dipanjan BASU ,  Richard FASTOW ,  Dimitri KIOUSSIS ,  Yi LI ,  Ebony Lynn MAYS ,  Dimitrios PAVLOPOULOS ,  Junyen TEWG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  G11C8/14

Abstract: A memory array including a varying width channel is disclosed. The array includes a plurality of WLs, which are above a layer, where the layer can be, for example, a Select Gate Source (SGS) of the memory array, or an isolation layer to isolate a first deck of the array from a second deck of the array. The channel extends through the plurality of word lines and at least partially through the layer. In an example, the channel comprises a first region and a second region. The first region of the channel has a first width that is at least 1 nm different from a second width of the second region of the channel. In an example, the first region extends through the plurality of word lines, and the second region extends through at least a part of the layer underneath the plurality of word lines. In one case, the first width is at least 1 nm less than a second width of the second region of the channel.

公开(公告)号：US20210328930A1

公开(公告)日：2021-10-21

申请号：US17359533

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Georgios NIKOLAIDIS ,  Jeremias BLENDIN ,  Changhoon KIM ,  Junggun LEE ,  Rong PAN ,  Anurag AGRAWAL ,  Yi LI

IPC: H04L12/801

Abstract: Examples described herein relate to an apparatus that includes a network interface device comprising circuitry to identify at least one congested queue, predict occupancy level of the at least one congested queue when at least one sender is predicted to receive at least one congestion notification and transmit the at least one congestion notification to the at least one sender through zero or more intermediate nodes. In some examples, to identify at least one congested queue, the circuitry is to identify the at least one congested queue based on at least one fill level. In some examples, to identify at least one congested queue, the circuitry is to identify the at least one congested queue based on at least one predicted fill level at a predicted time the at least one sender receives the at least one congestion notification.

公开(公告)号：US20210210478A1

公开(公告)日：2021-07-08

申请号：US17191615

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Susheel JADHAV ,  Juan DOMINGUEZ ,  Ankur AGRAWAL ,  Kenneth BROWN ,  Yi LI ,  Jing CHEN ,  Aditi MALLIK ,  Xiaoyu HONG ,  Thomas LILJEBERG ,  Andrew C. ALDUINO ,  Ling LIAO ,  David HUI ,  Ren-Kang CHIOU ,  Harinadh POTLURI ,  Hari MAHALINGAM ,  Lobna KAMYAB ,  Sasanka KANUPARTHI ,  Sushrutha Reddy GUJJULA ,  Saeed FATHOLOLOUMI ,  Priyanka DOBRIYAL ,  Boping XIE ,  Abiola AWUJOOLA ,  Vladimir TAMARKIN ,  Keith MEASE ,  Stephen KEELE ,  David SCHWEITZER ,  Brent ROTHERMEL ,  Ning TANG ,  Suresh POTHUKUCHI ,  Srikant NEKKANTY ,  Zhichao ZHANG ,  Kaiyuan ZENG ,  Baikuan WANG ,  Donald TRAN ,  Ravindranath MAHAJAN ,  Baris BICEN ,  Grant SMITH

IPC: H01L25/18 ,  H01L23/473 ,  H01R12/71

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonic engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonic engines are communicatively coupled to the die through the first package substrate and the second package substrate.