公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

申请人： Intel Corporation

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

摘要： Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US12002727B2

公开(公告)日：2024-06-04

申请号：US16788186

申请日：2020-02-11

申请人： INTEL CORPORATION

发明人： Ziyin Lin ,  Vipul Mehta ,  Wei Li ,  Edvin Cetegen ,  Xavier Brun ,  Yang Guo ,  Soud Choudhury ,  Shan Zhong ,  Christopher Rumer ,  Nai-Yuan Liu ,  Ifeanyi Okafor ,  Hsin-Wei Wang

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC分类号： H01L23/3185 ,  H01L23/3675 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/35121

摘要： An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

公开(公告)号：US11901333B2

公开(公告)日：2024-02-13

申请号：US16596367

申请日：2019-10-08

申请人： Intel Corporation

发明人： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US20200300911A1

公开(公告)日：2020-09-24

申请号：US16839238

申请日：2020-04-03

申请人： Intel Corporation

发明人： Vedvyas Shanbhogue ,  Jeff Huxel ,  Wei Li ,  Sanjoy Mondal ,  Arvind Raman

IPC分类号： G01R31/3187 ,  G06F1/3203 ,  G01R31/317 ,  G01R31/319 ,  G06F1/3234 ,  G06F11/00 ,  G06F11/34 ,  G06F11/07

摘要： In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

公开(公告)号：US10747884B2

公开(公告)日：2020-08-18

申请号：US15778980

申请日：2015-12-24

申请人： INTEL CORPORATION

发明人： Jiewen Yao ,  Vincent J. Zimmer ,  Wei Li ,  Rajesh Poornachandran ,  Giri P. Mudusuru

IPC分类号： G06F21/57 ,  G06F21/44 ,  G06F21/53 ,  G06F9/4401 ,  G06F9/54

摘要： Techniques for providing and maintaining protection of firmware routines that form part of a chain of trust through successive processing environments. An apparatus may include a first processor component (550); a volatile storage (562) coupled to the first processor component; an enclave component to, in a pre-OS operating environment, generate a secure enclave within a portion of the volatile storage to restrict access to a secured firmware loaded into the secure enclave; a first firmware driver (646) to, in the pre-OS operating environment, provide a first API to enable unsecured firmware to call a support routine of the secured firmware from outside the secure enclave; and a second firmware driver (647) to, in an OS operating environment that replaces the pre-OS operating environment, provide a second API to enable an OS of the OS operating environment to call the support routine from outside the secure enclave.

公开(公告)号：US12087731B2

公开(公告)日：2024-09-10

申请号：US18127539

申请日：2023-03-28

申请人： Intel Corporation

发明人： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC分类号： H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

摘要： Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US11935861B2

公开(公告)日：2024-03-19

申请号：US16862287

申请日：2020-04-29

申请人： Intel Corporation

发明人： Frederick W. Atadana ,  Taylor William Gaines ,  Edvin Cetegen ,  Wei Li ,  Hsin-Yu Li ,  Tony Dambrauskas

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/32 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/29 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0675 ,  H01L2924/0715

摘要： Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

公开(公告)号：US20190162782A1

公开(公告)日：2019-05-30

申请号：US15825352

申请日：2017-11-29

申请人： Intel Corporation

发明人： Vedvyas Shanbhogue ,  Jeff Huxel ,  Wei Li ,  Sanjoy Mondal ,  Arvind Raman

IPC分类号： G01R31/3187 ,  G01R31/319 ,  G01R31/317 ,  G06F1/32

摘要： In one embodiment, a processor includes at least one core and an interface circuit to interface the at least one core to additional circuitry of the processor. In response to an in-field self test instruction, at least one core may save state to a low power memory, enter into a diagnostic sleep state and execute an in-field self test in the diagnostic sleep state in which the at least one core appears to be inactive. Other embodiments are described and claimed.

公开(公告)号：US11942393B2

公开(公告)日：2024-03-26

申请号：US16781563

申请日：2020-02-04

申请人： Intel Corporation

发明人： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Mitul Modi ,  Nicholas Neal

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L23/3735 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/16 ,  H01L24/81 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2224/81203

摘要： Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

公开(公告)号：US11416603B2

公开(公告)日：2022-08-16

申请号：US16246187

申请日：2019-01-11

申请人： Intel Corporation

发明人： Zheng Zhang ,  Jason Martin ,  Justin Gottschlich ,  Abhilasha Bhargav-Spantzel ,  Salmin Sultana ,  Li Chen ,  Wei Li ,  Priyam Biswas ,  Paul Carlson

IPC分类号： G06F21/52 ,  G06N20/00 ,  G06F21/56 ,  G06F21/51 ,  G05B23/02

摘要： Methods, systems, articles of manufacture and apparatus to detect process hijacking are disclosed herein. An example apparatus to detect control flow anomalies includes a parsing engine to compare a target instruction pointer (TIP) address to a dynamic link library (DLL) module list, and in response to detecting a match of the TIP address to a DLL in the DLL module list, set a first portion of a normalized TIP address to a value equal to an identifier of the DLL. The example apparatus disclosed herein also includes a DLL entry point analyzer to set a second portion of the normalized TIP address based on a comparison between the TIP address and an entry point of the DLL, and a model compliance engine to generate a flow validity decision based on a comparison between (a) the first and second portion of the normalized TIP address and (b) a control flow integrity model.