发明授权
- 专利标题: No mold shelf package design and process flow for advanced package architectures
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申请号: US18127539申请日: 2023-03-28
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公开(公告)号: US12087731B2公开(公告)日: 2024-09-10
- 发明人: Wei Li , Edvin Cetegen , Nicholas S. Haehn , Ram S. Viswanath , Nicholas Neal , Mitul Modi
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 主分类号: H01L21/78
- IPC分类号: H01L21/78 ; H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L23/498 ; H01L25/065
摘要:
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
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