公开(公告)号：US11809878B2

公开(公告)日：2023-11-07

申请号：US16790203

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan Kumar

IPC: G06F9/445 ,  G06F13/16 ,  G06F16/22 ,  G06F9/4401 ,  G06F8/65

CPC classification number: G06F9/44505 ,  G06F8/65 ,  G06F9/4401 ,  G06F9/4411 ,  G06F13/1668 ,  G06F16/2228

Abstract: Systems, apparatuses and methods may provide for technology that stores first hardware related data to a basic input output system (BIOS) memory area and generates a mailbox data structure, wherein the mailbox data structure includes a first identifier-pointer pair associated with the first hardware related data. Additionally, the technology may generate an operating system (OS) interface table, wherein the OS interface table includes a pointer to the mailbox data structure. In one example, the technology also stores second hardware related data to the BIOS memory area at runtime and adds a second identifier-pointer pair to the mailbox data structure at runtime, wherein the second identifier-pointer pair is associated with the second hardware related data.

公开(公告)号：US11614939B2

公开(公告)日：2023-03-28

申请号：US17359337

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US10387072B2

公开(公告)日：2019-08-20

申请号：US15393935

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ashok Raj ,  Hemalatha Gurumoorthy ,  Ronald N. Story

IPC: G06F3/06 ,  G06F11/16 ,  G06F11/20

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

公开(公告)号：US20190227965A1

公开(公告)日：2019-07-25

申请号：US16369277

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar

IPC: G06F13/24

Abstract: A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.

公开(公告)号：US20180349231A1

公开(公告)日：2018-12-06

申请号：US15610067

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Subhankar Panda ,  Sarathy Jayakumar ,  Gaurav Porwal ,  Theodros Yigzaw

IPC: G06F11/14

CPC classification number: G06F11/0793 ,  G06F11/0772 ,  G06F11/0796 ,  G06F11/1415 ,  G06F11/142 ,  G06F11/1441

Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

公开(公告)号：US10078522B2

公开(公告)日：2018-09-18

申请号：US13977635

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F1/20 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F15/78 ,  G06F17/30 ,  G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/445 ,  G06F9/4401

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F16/2282 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US10019354B2

公开(公告)日：2018-07-10

申请号：US14100721

申请日：2013-12-09

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0866 ,  G06F12/0804

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1032 ,  G06F2212/7203

Abstract: Apparatus, systems, and methods to manage memory operations are described. A cache controller is provided comprising logic to receive a transaction to operate on a data element in a cache memory, determine whether the data element is to be stored in a nonvolatile memory by querying a source address decoder (SAD), and, in response to a determination that the data element is to be stored in the nonvolatile memory, to forward the transaction to a memory controller coupled to the nonvolatile memory, and, in response to a determination that the data element is not to be stored in the nonvolatile memory, to drop the transaction from a cache flush procedure of the cache controller. Additionally, the cache controller may receive a confirmation signal from the memory controller that the data element was stored in the nonvolatile memory, and return a completion signal to an originator of the transaction. The cache controller may also include logic to place a processor core in a low power state.

公开(公告)号：US09594570B2

公开(公告)日：2017-03-14

申请号：US13977625

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas

IPC: G06F11/00 ,  G06F9/44 ,  G06F17/30 ,  G06F9/445 ,  G06F1/28 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: Described is a computing platform, which comprises: a non-volatile memory having a firmware boot program; and a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create Power and Performance Measurement (PPM) interface data structures including an error injection table structure to provide error injection services to an OS.

Abstract translation: 描述了一种计算平台，其包括：具有固件引导程序的非易失性存储器; 以及CPU，当CPU被复位时执行固件引导程序，该固件引导程序包括用于创建功率和性能测量（PPM）接口数据结构的指令，该接口数据结构包括错误注入表结构以向OS提供错误注入服务。

公开(公告)号：US08762778B2

公开(公告)日：2014-06-24

申请号：US13891022

申请日：2013-05-09

Applicant: Intel Corporation

Inventor： Mohan Kumar ,  Sarathy Jayakumar

IPC: G06F11/00

CPC classification number: G06F11/34 ,  G06F11/0706 ,  G06F11/0769

Abstract: A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system.

Abstract translation: 已经公开了计算机系统中的固件辅助错误处理方案。 在一个实施例中，响应于系统管理中断（SMI）陷阱，固件用于访问计算机系统内的一个或多个硬件特定的错误寄存器。 使用固件，构建一个常见错误记录格式的错误记录。 错误记录可用于计算机系统内的操作系统（OS）。

公开(公告)号：US20240241805A1

公开(公告)日：2024-07-18

申请号：US18560270

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Tao Xu ,  Shijie Liu ,  Kevin Yufu Li ,  Lei Zhu ,  Sarathy Jayakumar

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F2201/85

Abstract: A disclosed example includes setting a corrected error threshold value for a memory rank; recording, in a corrected error bank record memory structure, corrected errors for memory banks in the memory rank; maintaining, in the corrected error bank record memory structure, counts of the corrected errors for the memory banks; and notifying runtime error handling circuitry in response to at least one of the counts of the corrected errors satisfying a threshold value.