-
公开(公告)号：US20180060078A1
公开(公告)日：2018-03-01
申请号：US15672254
申请日：2017-08-08
申请人： Intel Corporation
发明人： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V, Choubal , Scott D. Hahn , David A. Koufaty , Russel J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
-
公开(公告)号：US11275588B2
公开(公告)日：2022-03-15
申请号：US16624178
申请日：2017-07-01
申请人： Intel Corporation
IPC分类号： G06F9/30
摘要： Embodiments of an apparatus comprising a decoder to decode an instruction having fields for an opcode and a destination operand and execution circuitry to execute the decoded instruction to perform a save of processor state components to an area located at a destination memory address specified by the destination operand, wherein a size of the area is defined by at least one indication of an execution of an instruction operating on a specified group of processor states are described.
-
公开(公告)号：US09727345B2
公开(公告)日：2017-08-08
申请号：US13854001
申请日：2013-03-29
申请人： Intel Corporation
发明人： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russell J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
CPC分类号： G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
-
公开(公告)号：US12106100B2
公开(公告)日：2024-10-01
申请号：US16487421
申请日：2017-07-01
申请人： Intel Corporation
发明人： Robert Valentine , Mark J. Charney , Elmoustapha Ould-Ahmed-Vall , Dan Baum , Zeev Sperber , Jesus Corbal , Bret L. Toll , Raanan Sade , Igor Yanover , Yuri Gebil , Rinat Rappoport , Stanislav Shwartsman , Menachem Adelman , Simon Rubanovich
CPC分类号： G06F9/30036 , G06F7/485 , G06F7/4876 , G06F7/762 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30185 , G06F9/30196 , G06F9/3818 , G06F9/3836 , G06F17/16 , G06F2212/454
摘要： Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
-
公开(公告)号：US11567765B2
公开(公告)日：2023-01-31
申请号：US16487766
申请日：2017-07-01
申请人： Intel Corporation
发明人： Robert Valentine , Menachem Adelman , Milind B. Girkar , Zeev Sperber , Mark J. Charney , Bret L. Toll , Rinat Rappoport , Jesus Corbal , Stanislav Shwartsman , Dan Baum , Igor Yanover , Alexander F. Heinecke , Barukh Ziv , Elmoustapha Ould-Ahmed-Vall , Yuri Gebil
摘要： Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.
-
公开(公告)号：US20150193507A1
公开(公告)日：2015-07-09
申请号：US14127951
申请日：2013-08-06
申请人： INTEL CORPORATION
发明人： Rinat Rappoport , Raanan Yehezkel , Roman Fishtein , Sergei Goffman , Guy Jacob , Oren Gershon , Andrey Sloutsman , Ido Lapidot , Ofer Givoli
CPC分类号： G06F17/30528 , G06K9/00302 , G06Q10/101 , G06T2207/30201
摘要： Embodiments of techniques, apparatuses and systems associated with emotion information processing are disclosed. In some embodiments, a computing system may receive an image of a person and identify an emotional state of the person, based at least in part on the image. The computing system may cause storage of the emotional state of the person in combination with other data to enable subsequent response to an emotion-related query provided to the computing system. The emotion-related query may include an emotion-related criteria and a non-emotion-related criteria and the response may be based at least in part on the emotional state in combination with at least some of the other data. Other embodiments may be described and/or claimed.
摘要翻译： 公开了与情绪信息处理相关联的技术，装置和系统的实施例。 在一些实施例中，计算系统可以至少部分地基于图像来接收人的图像并且识别人的情绪状态。 计算系统可以使人的情绪状态与其他数据结合存储，以便能够随后响应提供给计算系统的情感相关查询。 情感相关查询可以包括情感相关标准和非情感相关标准，并且响应可以至少部分地基于情绪状态与至少一些其他数据的组合。 可以描述和/或要求保护其他实施例。
-
公开(公告)号：US11977886B2
公开(公告)日：2024-05-07
申请号：US17706413
申请日：2022-03-28
申请人： Intel Corporation
发明人： Robert Valentine , Menachem Adelman , Elmoustapha Ould-Ahmed-Vall , Bret L. Toll , Milind B. Girkar , Zeev Sperber , Mark J. Charney , Rinat Rappoport , Jesus Corbal , Stanislav Shwartsman , Igor Yanover , Alexander F. Heinecke , Barukh Ziv , Dan Baum , Yuri Gebil , Raanan Sade
CPC分类号： G06F9/30036 , G06F7/485 , G06F7/4876 , G06F7/762 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30185 , G06F9/30196 , G06F9/3818 , G06F9/3836 , G06F17/16 , G06F2212/454
摘要： Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.
-
公开(公告)号：US11714642B2
公开(公告)日：2023-08-01
申请号：US17706428
申请日：2022-03-28
申请人： Intel Corporation
发明人： Robert Valentine , Menachem Adelman , Elmoustapha Ould-Ahmed-Vall , Bret L. Toll , Milind B. Girkar , Zeev Sperber , Mark J. Charney , Rinat Rappoport , Jesus Corbal , Stanislav Shwartsman , Igor Yanover , Alexander F. Heinecke , Barukh Ziv , Dan Baum , Yuri Gebil
CPC分类号： G06F9/30036 , G06F7/485 , G06F7/4876 , G06F7/762 , G06F9/3001 , G06F9/3016 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30196 , G06F9/3818 , G06F9/3836 , G06F17/16 , G06F2212/454
摘要： Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.
-
公开(公告)号：US11080048B2
公开(公告)日：2021-08-03
申请号：US16487777
申请日：2017-07-01
申请人： Intel Corporation
发明人： Menachem Adelman , Robert Valentine , Zeev Sperber , Mark J. Charney , Bret L. Toll , Rinat Rappoport , Jesus Corbal , Dan Baum , Alexander F. Heinecke , Elmoustapha Ould-Ahmed-Vall , Yuri Gebil , Raanan Sade
摘要： Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
-
公开(公告)号：US20230409326A1
公开(公告)日：2023-12-21
申请号：US17841558
申请日：2022-06-15
申请人： Intel Corporation
发明人： Menachem Adelman , Amit Gradstein , Simon Rubanovich , Barukh Ziv , Uri Sherman , Dana Rip , Shahar Mizrahi , Dan Baum , Rinat Rappoport , Nilesh Jain , Zeev Sperber , Gideon Stupp , Alexander Heinecke , Christopher Hughes , Evangelos Georganas
CPC分类号： G06F9/30145 , G06F9/30178 , G06F9/30047 , G06F9/3887 , G06N3/04
摘要： Techniques and mechanisms for processor circuitry to execute a load and expand instruction of an instruction set to generate decompressed matrix data. In an embodiment, the instruction comprises a source operand which indicates a location from which compressed matrix data, and corresponding metadata, are to be accessed. A destination operand of the instruction indicates a location which is to receive decompressed metadata, which is generated, during execution of the instruction, based on the compressed matrix data and the corresponding metadata. The metadata comprises compression mask information which identifies which elements of the matrix have been masked from the compressed matrix data. In another embodiment, the instruction further comprises a count operand which identifies a total number of the unmasked matrix elements which are represented in the compressed matrix data.
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.016 秒)
