公开(公告)号：US10430193B2

公开(公告)日：2019-10-01

申请号：US15995736

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC: G06F9/30

Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US20180060078A1

公开(公告)日：2018-03-01

申请号：US15672254

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V, Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44 ,  G06F9/50 ,  G06F9/455

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：US20140189302A1

公开(公告)日：2014-07-03

申请号：US13993547

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Dheeraj R. Subbareddy ,  Ganapati N. Srinivasa ,  David A. Koufaty ,  Scott D. Hahn ,  Mishali Naik ,  Paolo Narvaez ,  Abirami Prabhakaran ,  Eugene Gorbatov ,  Alon Naveh ,  Inder M. Sodhi ,  Eliezer Weissmann ,  Paul Brett ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于在软件线程中并发执行的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

公开(公告)号：US10963257B2

公开(公告)日：2021-03-30

申请号：US16586977

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC: G06F9/30

Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US09639372B2

公开(公告)日：2017-05-02

申请号：US13730565

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

公开(公告)号：US09367314B2

公开(公告)日：2016-06-14

申请号：US13838450

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Edward Thomas Grochowski ,  Martin Guy Dixon ,  Yazmin A. Santiago ,  Mishali Naik

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30072

Abstract: A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The conditional short forward branch is to include a conditional branch instruction and a set of one or more instructions that are to sequentially follow the conditional branch instruction in program order. The set of the one or more instructions are between the conditional branch instruction and a forward branch target instruction that is to be indicated by the conditional branch instruction. The processor also includes instruction conversion logic coupled with the instruction fetch logic. The instruction conversion logic is to convert the conditional short forward branch to a computationally equivalent set of one or more predicated instructions. Other processors are also disclosed, as are various methods and systems.

Abstract translation: 处理器可操作以处理条件分支。 处理器包括用于获取条件短向前向分支的指令提取逻辑。 条件短路前进分支是包括一个条件分支指令和一组一个或多个指令，以顺序地按照程序顺序跟随条件分支指令。 一个或多个指令的集合在条件转移指令和由条件转移指令指示的前向转移目标指令之间。 处理器还包括与指令提取逻辑耦合的指令转换逻辑。 指令转换逻辑是将条件短前进分支转换成一个或多个预测指令的计算上等价的集合。 还公开了其他处理器，以及各种方法和系统。

公开(公告)号：US12039336B2

公开(公告)日：2024-07-16

申请号：US17898418

申请日：2022-08-29

Applicant: Intel Corporation

Inventor： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30018 ,  G06F9/30036

Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US11442734B2

公开(公告)日：2022-09-13

申请号：US17216580

申请日：2021-03-29

Applicant: Intel Corporation

Inventor： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC: G06F9/30

Abstract: A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US10228941B2

公开(公告)日：2019-03-12

申请号：US13931047

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Bret L. Toll ,  Ronak Singhal ,  Buford M. Guy ,  Mishali Naik

IPC: G06F9/30

Abstract: A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.

公开(公告)号：US10162687B2

公开(公告)日：2018-12-25

申请号：US13730800

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alon Naveh ,  Inder M. Sodhi ,  Ganapati N. Srinivasa ,  Eliezer Weissmann ,  Guarav Khanna ,  Mishali Naik ,  Russell J. Fenger ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy ,  David A. Koufaty ,  Paolo Narvaez

IPC: G06F9/50 ,  G06F1/32 ,  G06F1/20

Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.