公开(公告)号：US11294852B2

公开(公告)日：2022-04-05

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20180060078A1

公开(公告)日：2018-03-01

申请号：US15672254

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V, Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russel J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44 ,  G06F9/50 ,  G06F9/455

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：US20180285276A1

公开(公告)日：2018-10-04

申请号：US15476126

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Sanjay K. Kumar ,  Dheeraj R. Subbareddy ,  Jeffrey R. Jackson

IPC: G06F12/0873 ,  G06F17/30

CPC classification number: G06F12/0873 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0871 ,  G06F16/172 ,  G06F21/55 ,  G06F21/76 ,  G06F2212/1041 ,  G06F2212/225 ,  G06F2212/283 ,  G06F2212/608

Abstract: In one embodiment, an apparatus comprises a memory to store executable instructions of an operating system and a processor to identify a request for data from an application; determine whether a persistent page cache stores a copy of the data, wherein the persistent page cache is directly addressable by the processor and is to cache data of a storage device that is not directly addressable by the processor; and access the data from the persistent page cache.

公开(公告)号：US09672046B2

公开(公告)日：2017-06-06

申请号：US13730493

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Dheeraj R. Subbareddy ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Scott D. Hahn ,  David A. Koufaty ,  Paul Brett ,  Abirami Prabhakaran

IPC: G06F1/26 ,  G06F9/44 ,  G06F1/32 ,  G06F9/50 ,  G09G5/36

CPC classification number: G06F9/44 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  G09G5/363 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/24

Abstract: An intelligent power allocation architecture for a processor. For example, one embodiment of a processor comprises: a plurality of processor components for performing a corresponding plurality of processor functions; a plurality of power planes, each power plane associated with one of the processor components; and a power control unit (PCU) to dynamically adjust power to each of the power planes based on user experience metrics, workload characteristics, and power constraints for a current use of the processor.

公开(公告)号：US20160170645A1

公开(公告)日：2016-06-16

申请号：US14567662

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Dheeraj R. Subbareddy ,  Andrew V. Anderson

IPC: G06F3/06

CPC classification number: G06F12/0842 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/225 ,  G06F2212/601 ,  G06F2212/7201

Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

Abstract translation: 本文讨论了与永久存储器相关联的计算机可读存储介质，计算设备和方法。 在实施例中，计算设备可以包括一个或多个处理器，以及可以与一个或多个处理器耦合的多个持久存储模块。 计算设备还可以包括由一个或多个处理器操作的系统软件，以从一个或多个处理器执行的一个或多个应用接收易失性存储器分配请求和持久存储分配请求。 然后，响应于持久存储分配请求，系统软件可以响应于易失性存储器分配请求和持久类型存储器页面动态分配持久存储模块的存储器页面：易失性存储器页面。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10795853B2

公开(公告)日：2020-10-06

申请号：US15721822

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US09639372B2

公开(公告)日：2017-05-02

申请号：US13730565

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

公开(公告)号：US11586579B2

公开(公告)日：2023-02-21

申请号：US17513795

申请日：2021-10-28

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US09715453B2

公开(公告)日：2017-07-25

申请号：US14567662

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Dheeraj R. Subbareddy ,  Andrew V. Anderson

IPC: G06F3/06 ,  G06F12/0842 ,  G06F12/02 ,  G06F12/0897 ,  G06F12/1009

CPC classification number: G06F12/0842 ,  G06F12/0238 ,  G06F12/06 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/225 ,  G06F2212/601 ,  G06F2212/7201

Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

公开(公告)号：US20140189302A1

公开(公告)日：2014-07-03

申请号：US13993547

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Dheeraj R. Subbareddy ,  Ganapati N. Srinivasa ,  David A. Koufaty ,  Scott D. Hahn ,  Mishali Naik ,  Paolo Narvaez ,  Abirami Prabhakaran ,  Eugene Gorbatov ,  Alon Naveh ,  Inder M. Sodhi ,  Eliezer Weissmann ,  Paul Brett ,  Gaurav Khanna ,  Russell J. Fenger

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于在软件线程中并发执行的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。