公开(公告)号：US09507596B2

公开(公告)日：2016-11-29

申请号：US14471261

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Ashok Jagannathan ,  Prabhat Jain ,  Krishna N. Vinod ,  Avinash Sodani

IPC: G06F13/00 ,  G06F9/30 ,  G06F12/08 ,  G06F9/38 ,  G06F12/06

CPC classification number: G06F9/30047 ,  G06F9/383 ,  G06F9/3887 ,  G06F12/0646 ,  G06F12/0862 ,  G06F2212/6026 ,  G06F2212/6028

Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.

Abstract translation: 处理器包括核心，预取器和预取器控制模块。 预取器包括通过内存子系统进行推测预取请求的逻辑，用于由核心执行的元素，以及将预取元素存储在高速缓存中的逻辑。 预取器控制模块包括用于确定对两种类型的存储器的存储器访问的计数的逻辑，并且基于计数和存储器的类型，减少预取器的推测性预取请求。

公开(公告)号：US20160062768A1

公开(公告)日：2016-03-03

申请号：US14471261

申请日：2014-08-28

Applicant: Intel Corporation

Inventor： Ashok Jagannathan ,  Prabhat Jain ,  Krishna N. Vinod ,  Avinash Sodani

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30047 ,  G06F9/383 ,  G06F9/3887 ,  G06F12/0646 ,  G06F12/0862 ,  G06F2212/6026 ,  G06F2212/6028

Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.

Abstract translation: 处理器包括核心，预取器和预取器控制模块。 预取器包括用于通过存储器子系统进行推测预取请求的逻辑，用于由核心执行的元素以及将预取元素存储在高速缓存中的逻辑。 预取器控制模块包括用于确定对两种类型的存储器的存储器访问的计数的逻辑，并且基于计数和存储器的类型，减少预取器的推测性预取请求。

公开(公告)号：US10007620B2

公开(公告)日：2018-06-26

申请号：US15282841

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Seth H. Pugsley ,  Christopher B. Wilkerson ,  Roger Gramunt ,  Jonathan C. Hall ,  Prabhat Jain

IPC: G06F12/00 ,  G06F12/121 ,  G06F12/0864 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862

CPC classification number: G06F12/126 ,  G06F1/3275 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/70 ,  Y02D10/14

Abstract: A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.

公开(公告)号：US20180095895A1

公开(公告)日：2018-04-05

申请号：US15282841

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Seth H. Pugsley ,  Christopher B. Wilkerson ,  Roger Gramunt ,  Jonathan C. Hall ,  Prabhat Jain

IPC: G06F12/121 ,  G06F12/0864

CPC classification number: G06F12/121 ,  G06F1/3275 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/6042 ,  G06F2212/69 ,  G06F2212/70

Abstract: A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.