公开(公告)号：US20240312853A1

公开(公告)日：2024-09-19

申请号：US18121331

申请日：2023-03-14

申请人： Intel Corporation

发明人： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

摘要： Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240105575A1

公开(公告)日：2024-03-28

申请号：US17953206

申请日：2022-09-26

申请人： Intel Corporation

发明人： Jason M. GAMBA ,  Haifa HARIRI ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Hiroki TANAKA ,  Kyle MCELHINNY ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Haobo CHEN ,  Bai NIE ,  Numair AHMED

IPC分类号： H01L23/498 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/12 ,  H01L21/48

CPC分类号： H01L23/49838 ,  C25D3/12 ,  C25D3/48 ,  C25D3/50 ,  C25D7/123 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49866 ,  H01L24/16

摘要： Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

公开(公告)号：US20220199503A1

公开(公告)日：2022-06-23

申请号：US17129846

申请日：2020-12-21

申请人： Intel Corporation

发明人： Manish DUBEY ,  Guruprasad ARAKERE ,  Deepak KULKARNI ,  Sairam AGRAHARAM ,  Wei-Lun K. JEN ,  Numair AHMED ,  Kousik GANESAN ,  Amol D. JADHAV ,  Kyu-Oh LEE

IPC分类号： H01L23/498 ,  H01L21/48

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.

公开(公告)号：US20220165695A1

公开(公告)日：2022-05-26

申请号：US17104919

申请日：2020-11-25

申请人： Intel Corporation

发明人： Numair AHMED ,  Kyu-Oh LEE ,  Brandon C. MARIN ,  Gang DUAN

IPC分类号： H01L23/00 ,  H01L23/498

摘要： Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.

公开(公告)号：US20240312888A1

公开(公告)日：2024-09-19

申请号：US18121264

申请日：2023-03-14

申请人： Intel Corporation

发明人： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838

摘要： Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20200312803A1

公开(公告)日：2020-10-01

申请号：US16363996

申请日：2019-03-25

申请人： Intel Corporation

发明人： Jimin YAO ,  Shawna LIFF ,  Xin YAN ,  Numair AHMED

IPC分类号： H01L23/00

摘要： Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.