- 专利标题: POROUS FLI BUMPS FOR REDUCING BUMP THICKNESS VARIATION SENSITIVITY TO ENABLE BUMP PITCH SCALING
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申请号: US17104919申请日: 2020-11-25
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公开(公告)号: US20220165695A1公开(公告)日: 2022-05-26
- 发明人: Numair AHMED , Kyu-Oh LEE , Brandon C. MARIN , Gang DUAN
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L23/00
- IPC分类号: H01L23/00 ; H01L23/498
摘要:
Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.
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