公开(公告)号：US10319461B2

公开(公告)日：2019-06-11

申请号：US15197590

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Kon-Woo Kwon ,  Vivek Kozhikkottu ,  Dinesh Somasekhar

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11C29/02 ,  G11C29/42

Abstract: Embodiments are generally directed to a low-overhead mechanism to detect address faults in ECC-protected memories. An embodiment of an apparatus includes a memory array; an error correction code (ECC) encoder for the memory array to encode ECC values based on a data value and a respective address value for the data value; and an ECC decoder for the memory array to decode ECC values that are based on data values and respective addresses for the data values; wherein the apparatus is to detect and correct an error in an address value based on an ECC value, address value, and data value stored in the memory.

公开(公告)号：US10853300B2

公开(公告)日：2020-12-01

申请号：US15475571

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

公开(公告)号：US20200313694A1

公开(公告)日：2020-10-01

申请号：US16367511

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Wei Wu ,  Vivek Kozihikkottu ,  Dinesh Somasekhar ,  Jon Stephan ,  Kon-Woo Kwon

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/15

Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K−2(K−1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.

公开(公告)号：US20180285304A1

公开(公告)日：2018-10-04

申请号：US15475571

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

公开(公告)号：US20180285252A1

公开(公告)日：2018-10-04

申请号：US15477072

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Kon-Woo Kwon ,  Vivek Kozhikkottu ,  Sang Phill Park ,  Ankit More ,  William P. Griffin ,  Robert Pawlowski ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F12/02 ,  G06F12/0802 ,  G06F12/0846 ,  G11C7/10 ,  G06F12/06

Abstract: Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data are disclosed and described. A system memory is divided into a plurality of memory subsections, where each memory subsection is communicatively coupled to an independent memory channel to a memory controller. Memory access requests from a processor are thereby sent by the memory controller to only the appropriate memory subsection.