公开(公告)号：US10296338B2

公开(公告)日：2019-05-21

申请号：US15373668

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Brent R. Boswell ,  Banu Meenakshi Nagasundaram ,  Michael D. Abbott ,  Srikanth Dakshinamoorthy ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an alternate address space configuration register to store configuration information to enable the core to execute instructions from the first address space; and a control logic to configure the core based in part on information in the alternate address space configuration register. Other embodiments are described and claimed.

公开(公告)号：US10795819B1

公开(公告)日：2020-10-06

申请号：US16453670

申请日：2019-06-26

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Bharadwaj Krishnamurthy ,  Vincent Cave ,  Jason M. Howard ,  Ankit More ,  Joshua B. Fryman

IPC: G06F12/00 ,  G06F12/0817 ,  G06F12/0811 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0891

Abstract: Disclosed embodiments relate to a system with configurable cache sub-domains and cross-die memory coherency. In one example, a system includes R racks, each rack housing N nodes, each node incorporating D dies, each die containing C cores and a die shadow tag, each core including P pipelines and a core shadow tag, each pipelines associated with a data cache and data cache tags and being either non-coherent or coherent and one of X coherency domains, wherein each pipeline, when needing to read a cache line, issues a read request to its associated data cache, then, if need be, issues a read request to its associated core-level cache, then, if need be, issues a read request to its associated die-level cache, then, if need be, issues a no-cache remote read request to a target die being mapped to hold the cache line.

公开(公告)号：US20220100508A1

公开(公告)日：2022-03-31

申请号：US17134251

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Ankit More ,  Vincent Cave ,  Sriram Aananthakrishnan ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments of apparatuses and methods for copying and operating on matrix elements are described. In embodiments, an apparatus includes a hardware instruction decoder to decode a single instruction and execution circuitry, coupled to hardware instruction decoder, to perform one or more operations corresponding to the single instruction. The single instruction has a first operand to reference a base address of a first representation of a source matrix and a second operand to reference a base address of second representation of a destination matrix. The one or more operations include copying elements of the source matrix to corresponding locations in the destination matrix and filling empty elements of the destination matrix with a single value.

公开(公告)号：US20190109590A1

公开(公告)日：2019-04-11

申请号：US16201915

申请日：2018-11-27

Applicant: Intel Corporation

Inventor： Ankit More ,  Jason M. Howard ,  Robert Pawlowski ,  Fabrizio Petrini ,  Shaden Smith

IPC: H03K17/00 ,  H03K19/173 ,  G11C7/10

CPC classification number: H03K17/005 ,  G11C7/1006 ,  H03K17/007 ,  H03K19/1733

Abstract: Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.

公开(公告)号：US20180285252A1

公开(公告)日：2018-10-04

申请号：US15477072

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Kon-Woo Kwon ,  Vivek Kozhikkottu ,  Sang Phill Park ,  Ankit More ,  William P. Griffin ,  Robert Pawlowski ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F12/02 ,  G06F12/0802 ,  G06F12/0846 ,  G11C7/10 ,  G06F12/06

Abstract: Optimized memory access bandwidth devices, systems, and methods for processing low spatial locality data are disclosed and described. A system memory is divided into a plurality of memory subsections, where each memory subsection is communicatively coupled to an independent memory channel to a memory controller. Memory access requests from a processor are thereby sent by the memory controller to only the appropriate memory subsection.

公开(公告)号：US11960922B2

公开(公告)日：2024-04-16

申请号：US17030999

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Joshua B. Fryman ,  Jason M. Howard ,  Ibrahim Hur ,  Robert Pawlowski

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06Q10/101

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3834 ,  G06F2212/452 ,  G06Q10/101

Abstract: In an embodiment, a processor comprises: an execution circuit to execute instructions; at least one cache memory coupled to the execution circuit; and a table storage element coupled to the at least one cache memory, the table storage element to store a plurality of entries each to store object metadata of an object used in a code sequence. The processor is to use the object metadata to provide user space multi-object transactional atomic operation of the code sequence. Other embodiments are described and claimed.

公开(公告)号：US11106494B2

公开(公告)日：2021-08-31

申请号：US16147302

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Ankit More ,  Jason M. Howard ,  Joshua B. Fryman ,  Tina C. Zhong ,  Shaden Smith ,  Sowmya Pitchaimoorthy ,  Samkit Jain ,  Vincent Cave ,  Sriram Aananthakrishnan ,  Bharadwaj Krishnamurthy

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0815 ,  G06F9/35 ,  G06F13/28

Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.

公开(公告)号：US11061742B2

公开(公告)日：2021-07-13

申请号：US16019685

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Ankit More ,  Shaden Smith ,  Sowmya Pitchaimoorthy ,  Samkit Jain ,  Vincent Cavé ,  Sriram Aananthakrishnan ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a first processor core includes: a plurality of execution pipelines each to execute instructions of one or more threads; a plurality of pipeline barrier circuits coupled to the plurality of execution pipelines, each of the plurality of pipeline barrier circuits associated with one of the plurality of execution pipelines to maintain status information for a plurality of barrier groups, each of the plurality of barrier groups formed of at least two threads; and a core barrier circuit to control operation of the plurality of pipeline barrier circuits and to inform the plurality of pipeline barrier circuits when a first barrier has been reached by a first barrier group of the plurality of barrier groups. Other embodiments are described and claimed.

公开(公告)号：US20200004602A1

公开(公告)日：2020-01-02

申请号：US16019685

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Ankit More ,  Shaden Smith ,  Sowmya Pitchaimoorthy ,  Samkit Jain ,  Vincent Cavé ,  Sriram Aananthakrishnan ,  Jason M. Howard ,  Joshua B. Fryman

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/30

Abstract: In one embodiment, a first processor core includes: a plurality of execution pipelines each to execute instructions of one or more threads; a plurality of pipeline barrier circuits coupled to the plurality of execution pipelines, each of the plurality of pipeline barrier circuits associated with one of the plurality of execution pipelines to maintain status information for a plurality of barrier groups, each of the plurality of barrier groups formed of at least two threads; and a core barrier circuit to control operation of the plurality of pipeline barrier circuits and to inform the plurality of pipeline barrier circuits when a first barrier has been reached by a first barrier group of the plurality of barrier groups. Other embodiments are described and claimed.

公开(公告)号：US11630691B2

公开(公告)日：2023-04-18

申请号：US17410818

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Ankit More ,  Jason M. Howard ,  Joshua B. Fryman ,  Tina C. Zhong ,  Shaden Smith ,  Sowmya Pitchaimoorthy ,  Samkit Jain ,  Vincent Cave ,  Sriram Aananthakrishnan ,  Bharadwaj Krishnamurthy

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/48 ,  G06F12/0815 ,  G06F9/38 ,  G06F13/28

Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.