公开(公告)号：US20200313694A1

公开(公告)日：2020-10-01

申请号：US16367511

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Wei Wu ,  Vivek Kozihikkottu ,  Dinesh Somasekhar ,  Jon Stephan ,  Kon-Woo Kwon

IPC: H03M13/11 ,  H03M13/00 ,  H03M13/15

Abstract: In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K−2(K−1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.