公开(公告)号：US20250112175A1

公开(公告)日：2025-04-03

申请号：US18477638

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Jesse C. Jones ,  Yosef Kornbluth ,  Mitchell Page ,  Soham Agarwal ,  Fanyi Zhu ,  Shuren Qu ,  Hanyu Song ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Bai Nie ,  Nicholas Haehn ,  Astitva Tripathi ,  Mohamed R. Saber ,  Sheng Li ,  Pratyush Mishra ,  Benjamin T. Duong ,  Kari Hernandez ,  Praveen Sreeramagiri ,  Yi Li ,  Ibrahim El Khatib ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Haobo Chen ,  Robin Shea McRee ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L25/065

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

公开(公告)号：US20240096561A1

公开(公告)日：2024-03-21

申请号：US17948586

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Benjamin Duong ,  Shayan Kaviani ,  Joshua Stacey ,  Miranda Ngan ,  Dilan Seneviratne ,  Thomas Heaton ,  Srinivas Venkata Ramanuja Pietambaram ,  Whitney Bryks ,  Jieying Kong

IPC: H01G4/33 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01L28/92 ,  H01L25/16

Abstract: An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.

公开(公告)号：US12266581B2

公开(公告)日：2025-04-01

申请号：US17085177

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Whitney Bryks ,  Sarah Blythe ,  Peumie Abeyratne Kuragama ,  Junxin Wang

IPC: H01L23/18 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522

Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.

公开(公告)号：US20240222295A1

公开(公告)日：2024-07-04

申请号：US18148598

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Joshua Stacey ,  Benjamin T. Duong ,  Thomas S. Heaton ,  Dilan Seneviratne ,  Rahul N. Manepalli

IPC: H01L23/64 ,  H01G4/20 ,  H01G4/33 ,  H01L23/00 ,  H01L23/498 ,  H05K1/16

CPC classification number: H01L23/642 ,  H01G4/206 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H05K1/162 ,  H01L2224/16235 ,  H01L2924/19041 ,  H05K2201/0175

Abstract: Embodiments described herein enable a microelectronic assembly that includes: a package substrate having a core including a solid continuous glass material with one or more capacitors in the solid continuous glass material and integrated circuit (IC) dies coupled to the package substrate. The structure of each capacitor includes a dielectric structure between two conductive structures. The dielectric structure comprises a layer of organic dielectric material between two layers of crystalline inorganic material. The crystalline inorganic material is in direct contact with one of the two conductive structures.

公开(公告)号：US20220139792A1

公开(公告)日：2022-05-05

申请号：US17085177

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Whitney Bryks ,  Sarah Blythe ,  Peumie Abeyratne Kuragama ,  Junxin Wang

IPC: H01L23/29 ,  H01L23/18 ,  H01L23/31 ,  H01L23/522

Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.

公开(公告)号：US20250112163A1

公开(公告)日：2025-04-03

申请号：US18375203

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Pratyasha Mohapatra ,  Srinivas Pietambaram ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Yosef Kornbluth ,  Kuang Liu ,  Astitva Tripathi ,  Yuqin Li ,  Rengarajan Shanmugam ,  Xing Sun ,  Brian Balch ,  Darko Grujicic ,  Jieying Kong ,  Nicholas Haehn ,  Jacob Vehonsky ,  Mitchell Page ,  Vincent Obiozo Eze ,  Daniel Wandera ,  Sameer Paital ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L25/065

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.

公开(公告)号：US12214579B2

公开(公告)日：2025-02-04

申请号：US17949276

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Yosef Kornbluth ,  Whitney Bryks

IPC: B32B41/00 ,  B32B37/06 ,  B32B37/08 ,  B32B37/10 ,  H01L21/48

Abstract: The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.