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公开(公告)号：US10037227B2
公开(公告)日：2018-07-31
申请号：US14973009
申请日：2015-12-17
Applicant: INTEL CORPORATION
Inventor： Guy Therien , Guy Sotomayor , Arijit Biswas , Michael D. Powell , Eric J. Dehaemer
IPC: G06F9/46 , G06F9/48 , G06F1/32 , G06F9/50 , G06F9/4401
CPC classification number: G06F9/4856 , G06F1/3287 , G06F9/4418 , G06F9/461 , G06F9/4893 , G06F9/5094 , Y02D10/24 , Y02D10/32 , Y02D10/44
Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
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公开(公告)号：US20240281405A1
公开(公告)日：2024-08-22
申请号：US18172943
申请日：2023-02-22
Applicant: Intel Corporation
Inventor： Guy Therien
CPC classification number: G06F15/7882 , G06F1/28
Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions and a non-volatile storage coupled to the plurality of cores to store identification information regarding the plurality of cores, the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. The processor is specified with a first subset of the plurality of cores comprising assured cores and a second subset of the plurality of cores comprising opportunistic cores, and is to execute, within a specified power budget and a specified thermal budget, a specified workload on the first subset of the plurality of cores at a first performance level. Other embodiments are described and claimed.
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公开(公告)号：US20190042307A1
公开(公告)日：2019-02-07
申请号：US16117091
申请日：2018-08-30
Applicant: Intel Corporation
Inventor： Ramakrishnan Sivakumar , Vijay Dhanraj , Russell Fenger , Guy Therien
Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.
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公开(公告)号：US20220197367A1
公开(公告)日：2022-06-23
申请号：US17127899
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Deepak S Kirubakaran , Ramakrishnan Sivakumar , Russell Fenger , Monica Gupta , Jianwei Dai , Premanand Sakarda , Guy Therien , Rajshree Chabukswar , Chad Gutierrez , Renji Thomas
IPC: G06F1/3287 , G06F1/3228
Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.
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公开(公告)号：US20190102227A1
公开(公告)日：2019-04-04
申请号：US15720222
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Avinash Ananthakrishnan , Vijay Dhanraj , Russell Fenger , Vivek Garg , Eugene Gorbatov , Stephen Gunter , Monica Gupta , Efraim Rotem , Krishnakanth Sistla , Guy Therien , Ankush Verma , Eliezer Weissmann
Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20190065242A1
公开(公告)日：2019-02-28
申请号：US16048570
申请日：2018-07-30
Applicant: INTEL CORPORATION
Inventor： Guy Therien , Guy Sotomayor , Arijit Biswas , Michael D. Powell , Eric J. Dehaemer
IPC: G06F9/48 , G06F9/50 , G06F9/46 , G06F9/4401 , G06F1/32
Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
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公开(公告)号：US20180324356A1
公开(公告)日：2018-11-08
申请号：US15773969
申请日：2015-11-16
Applicant: INTEL CORPORATION
Inventor： Rajiva K. Sarraju , Joshua L. Zuniga , Aleksander Magi , David W. Browning , Audrey C. Younkin , Saara Kamppari-Miller , Phil Riehl , Guy Therien
CPC classification number: H04N5/23245 , G06F1/1626 , G06F1/1641 , G06F1/1652 , G06F1/1677 , G06F1/1686 , H04N5/2257 , H04N5/2258 , H04N5/23293 , H04N5/232945 , H04N5/23296 , H04N5/247
Abstract: The present disclosure pertains to extended visual capture in a reconfigurable device. In general, at least a display portion of a device may have a deformable shape configuration in that its shape is changeable by a user. The device may also comprise at least sensor circuitry including a plurality of sensors. The shape configuration may position the plurality of sensors at different positions to enable extended visual capture of a 180 to 360 degree viewing range surrounding the device in a single image or video. Control circuitry in the device may determine when shape reconfiguration of at least the display has occurred, determine whether the new shape configuration involves visual capture, and if the new shape configuration is determined to involve visual capture, determine an operational mode for the at least the sensor circuitry and cause the sensor circuitry to capture visual data based at least on the operational mode.
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公开(公告)号：US20170177407A1
公开(公告)日：2017-06-22
申请号：US14973009
申请日：2015-12-17
Applicant: INTEL CORPORATION
Inventor： Guy Therien , Guy Sotomayor , Arijit Biswas , Michael D. Powell , Eric J. Dehaemer
CPC classification number: G06F9/4856 , G06F1/3287 , G06F9/4418 , G06F9/461 , G06F9/4893 , G06F9/5094 , Y02D10/24 , Y02D10/32 , Y02D10/44
Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
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公开(公告)号：US09348401B2
公开(公告)日：2016-05-24
申请号：US13926025
申请日：2013-06-25
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Paul Diefenbaugh , Guy Therien , Nir Rosenzweig
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3243 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/152
Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元（PCU），以控制处理器的功率消耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能标度值，并且至少部分地基于性能标度值来计算动态性能 - 频率映射。 描述和要求保护其他实施例。
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公开(公告)号：US12141015B2
公开(公告)日：2024-11-12
申请号：US17127899
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Deepak S Kirubakaran , Ramakrishnan Sivakumar , Russell Fenger , Monica Gupta , Jianwei Dai , Premanand Sakarda , Guy Therien , Rajshree Chabukswar , Chad Gutierrez , Renji Thomas
IPC: G06F1/3287 , G06F1/3228
Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.
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