公开(公告)号：US09262163B2

公开(公告)日：2016-02-16

申请号：US13730834

申请日：2012-12-29

申请人： Intel Corporation

发明人： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/30

CPC分类号： G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

摘要翻译： 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。

公开(公告)号：US09996127B2

公开(公告)日：2018-06-12

申请号：US14207074

申请日：2014-03-12

申请人： Intel Corporation

发明人： Omer Vikinski ,  Igor Yanover ,  Gavri Berger ,  Gabi Malka ,  Zeev Sperber

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F9/50

CPC分类号： G06F1/26 ,  G06F1/28 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

摘要： A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

公开(公告)号：US20160117171A1

公开(公告)日：2016-04-28

申请号：US14992658

申请日：2016-01-11

申请人： INTEL CORPORATION

发明人： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

IPC分类号： G06F9/30 ,  G06F13/40

CPC分类号： G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

摘要翻译： 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。

公开(公告)号：US09716646B2

公开(公告)日：2017-07-25

申请号：US14334071

申请日：2014-07-17

申请人： Intel Corporation

发明人： Tsvika Kurts ,  Beeman C. Strong ,  Ofer Levy ,  Gabi Malka ,  Zeev Sperber

IPC分类号： H04L7/00 ,  H04L12/26 ,  H04J3/06

CPC分类号： H04L43/50 ,  H04J3/0664 ,  H04L43/106

摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

公开(公告)号：US09696997B2

公开(公告)日：2017-07-04

申请号：US14992658

申请日：2016-01-11

申请人： INTEL CORPORATION

发明人： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

IPC分类号： G06F9/00 ,  G06F7/38 ,  G06F9/30 ,  G06F11/00 ,  G06F11/36 ,  G06F11/34 ,  G06F13/40

CPC分类号： G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.