-
公开(公告)号：US20240110975A1
公开(公告)日：2024-04-04
申请号：US17958071
申请日：2022-09-30
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Vladislav Mladentsev , Elias Khoury , Rakesh Kandula , Reuven Elbaum , Boris Dolgunov
IPC: G01R31/317 , H04L9/08 , H04L9/32 , H04L9/40
CPC classification number: G01R31/31719 , H04L9/0819 , H04L9/0866 , H04L9/0869 , H04L9/3213 , H04L63/0428
Abstract: Methods and apparatus relating to techniques to provide secure remote debugging are described. In an embodiment, a debugging entity generates and transmits a host token to a device via an interface. The interface provides encrypted communication between the debugging entity and the device. The debugging entity generates a session key based at least in part on the host token and a device token. The debugging entity transmits an acknowledgement signal to the device after generation of the session key to initiate a debug session. The debugging entity transmits a debug unlock key to the device to cause the device to be unlocked for the debug session. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US11544174B2
公开(公告)日：2023-01-03
申请号：US16832353
申请日：2020-03-27
Applicant: INTEL CORPORATION
Inventor： Loren James McConnell , Tsvika Kurts , Boris Dolgunov , Vamsi Krishna Jakkampudi , Marcus Winston , Kevin David Safford
Abstract: Methods and apparatus for protecting trace data of a remote debug session for a computing system. In one embodiment, a method includes storing trace data received from one or more trace interfaces to a storage location of a target device, where the trace data is generated from execution at the target device, and where the trace data is protected from an unauthorized access. The method continues with transmitting the trace data to a debug host computer with encryption through a communication channel between the target device and the debug host computer.
-
公开(公告)号：US12130724B2
公开(公告)日：2024-10-29
申请号：US16912545
申请日：2020-06-25
Applicant: Intel Corporation
Inventor： Gilad Shayevitz , Tsvika Kurts , Vladislav Kopzon , Reuven Rozic , Yaniv Hayat
CPC classification number: G06F11/3636 , G06F11/3476 , G06F11/3688 , G06F11/3692 , G06F13/385 , G06F13/4282
Abstract: A system can include a host machine connected to a device under test (DUT) by a serial link. The host machine can include a serial interface, such as a Thunderbolt interface, and a memory. The DUT can include a trace data source, a high-speed trace interface (HTI) to receive trace data from the trace data source, a serial interface (such as a Thunderbolt interface), and a PIPE interface connecting the HTI with the serial interface. The HTI is to send the trace data to the serial interface through the PIPE interface. The serial interface is to packetize the trace data into a conforming packet format, and send the trace data as a packet across the serial link to the host machine. The host machine can receive the trace data at the host-side serial interface, store the trace data in memory, and process the trace data for debugging the DUT.
-
公开(公告)号：US20160117171A1
公开(公告)日：2016-04-28
申请号：US14992658
申请日：2016-01-11
Applicant: INTEL CORPORATION
Inventor： Tsvika Kurts , Ofer Levy , Itamar Kazachinsky , Gabi Malka , Zeev Sperber , Jason W. Brandt
CPC classification number: G06F9/30145 , G06F11/00 , G06F11/3471 , G06F11/36 , G06F13/4068 , G06F2201/865
Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.
Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。
-
公开(公告)号：US10725848B2
公开(公告)日：2020-07-28
申请号：US15890893
申请日：2018-02-07
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Ki W. Yoon , Michael J. St. Clair , Larisa Novakovsky , Hisham Shafi , William H. Penner , Yoni Aizik , Kevin Safford , Hermann Gartler
Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.
-
Patent Agency Ranking
公开(公告)号：US09870301B2
公开(公告)日：2018-01-16
申请号：US14231240
申请日：2014-03-31
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Eilon Hazan , Sean T. Baartmans , Marcus R. Winston , Rony Ghattas , Arie Bernstein , Todd M. Witter , Marcelo Yuffe
CPC classification number: G06F11/3476 , G06F11/3024 , G06F11/323 , G06F11/3409 , G06F11/3466 , G06F11/3636 , G06F11/3656
Abstract: A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in a first mode or a second mode and to collect trace information comprising operating characteristics of the processing device. The processing device further comprises a display engine logic to process display data for output to a display device. In addition, the processing device comprises a display engine interface to provide, to a plurality of existing platform connectors, the display data from the display engine logic when the processing device is operating in the first primary mode and the trace information from the debug port controller when the processing device is operating in the second mode as determined by the debug port controller.
-
公开(公告)号：US09660799B1
公开(公告)日：2017-05-23
申请号：US14950319
申请日：2015-11-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Ernest Knoll , Ofer Nathan , Michael Mishaeli , Krishnakanth V. Sistla , Ariel Sabba , Shani Rehana , Ariel Szapiro , Tsvika Kurts , Ofer Levy
CPC classification number: H04L7/0331 , G06F1/08 , G06F1/10 , G06F1/324 , H04L7/0025 , H04L7/005 , Y02D10/126
Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.
-
公开(公告)号：US11754623B2
公开(公告)日：2023-09-12
申请号：US17397951
申请日：2021-08-09
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Boris Dolgunov , Vladislav Mladentsev , Ittai Anati , Elias Khoury , Maor Kima , Eran Shlomo , Shay Gueron , William Penner
IPC: G01R31/317 , G06F16/22 , G01R31/3177 , G06F11/263 , H04L9/06 , H04L9/08 , H04L9/32
CPC classification number: G01R31/31719 , G01R31/3177 , G01R31/31705 , G06F11/263 , G06F16/22 , H04L9/0631 , H04L9/0819 , H04L9/0894 , H04L9/321
Abstract: Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.
-
公开(公告)号：US20210364571A1
公开(公告)日：2021-11-25
申请号：US17397951
申请日：2021-08-09
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Boris Dolgunov , Vladislav Mladentsev , Ittai Anati , Elias Khoury , Maor Kima , Eran Shlomo , Shay Gueron , William Penner
IPC: G01R31/317 , G06F16/22 , G01R31/3177 , G06F11/263 , H04L9/06 , H04L9/08 , H04L9/32
Abstract: Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.
-
公开(公告)号：US20200349312A1
公开(公告)日：2020-11-05
申请号：US16854788
申请日：2020-04-21
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Alexander Gendler , Larisa Novakovsky , Anwar Azaarura Zaa'Rura , Afik Sela , Genadi Kazakevich , Alexandra Shainshein , Ariel Sabba
IPC: G06F30/3323 , G01R31/317 , G06F11/30 , G06F11/34 , G06F11/36
Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.016 seconds)
