公开(公告)号：US20250052809A1

公开(公告)日：2025-02-13

申请号：US18233199

申请日：2023-08-11

Applicant: Intel Corporation

Inventor： Fei Su ,  Rakesh Kandula

IPC: G01R31/28 ,  G01R31/317

Abstract: Techniques and mechanisms for an integrated circuit (IC) die to support in-field testing and/or repair of a lane in a three-dimensional (3D) IC which is formed with multiple IC dies. In an embodiment, the 3D IC comprises test units which each correspond to a different partition comprising respective circuit resources. During in-field operation of the 3D IC, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second condition wherein a first link between the two partitions fails to satisfy a performance criteria. The idle states are indicated by a power management controller (PMC) agent during runtime operation of the 3D IC. In another embodiment, one or more test units configure an operational mode, based on the detected conditions, to substitute communication via the first lane with communication via a repair lane.

公开(公告)号：US20240427975A1

公开(公告)日：2024-12-26

申请号：US18340662

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Rakesh Kandula ,  Srinivasa Ramakrishna STG

IPC: G06F30/3315 ,  G06F1/04

Abstract: Methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. An example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (SoC) architecture, obtain a timing assertion associated with the SoC architecture, determine, using a formal property verification (FPV) tool, valid functional vectors and counter examples for the SoC architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.

公开(公告)号：US20240385946A1

公开(公告)日：2024-11-21

申请号：US18197255

申请日：2023-05-15

Applicant: Intel Corporation

Inventor： Rakesh Kandula ,  Rolf Kuehnis ,  Sankaran Menon

IPC: G06F11/36

Abstract: An example of an apparatus may include circuitry to monitor one or more sensors, determine a debug condition based on the monitored one or more sensors, and provide an indication of the debug condition. In some examples, the apparatus includes further circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition. Other examples are disclosed and claimed.

公开(公告)号：US20240220312A1

公开(公告)日：2024-07-04

申请号：US18091810

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Rakesh Kandula ,  Shlomo Avni ,  Fei Su

IPC: G06F9/48 ,  G06F11/263

CPC classification number: G06F9/4812 ,  G06F11/263

Abstract: Methods and apparatus relating to intelligent sensors for high quality silicon life cycle management as well as efficient infield structural and/or functional testing are described. In an embodiment, one or more registers store configuration data. A sensor having sensor event detection logic circuitry detects an event based at least in part on one or more sensor signals and the stored configuration data. The sensor event detection logic circuitry generates a signal to cause interrupt generator logic circuitry of the sensor to generate an interrupt. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240110975A1

公开(公告)日：2024-04-04

申请号：US17958071

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Vladislav Mladentsev ,  Elias Khoury ,  Rakesh Kandula ,  Reuven Elbaum ,  Boris Dolgunov

IPC: G01R31/317 ,  H04L9/08 ,  H04L9/32 ,  H04L9/40

CPC classification number: G01R31/31719 ,  H04L9/0819 ,  H04L9/0866 ,  H04L9/0869 ,  H04L9/3213 ,  H04L63/0428

Abstract: Methods and apparatus relating to techniques to provide secure remote debugging are described. In an embodiment, a debugging entity generates and transmits a host token to a device via an interface. The interface provides encrypted communication between the debugging entity and the device. The debugging entity generates a session key based at least in part on the host token and a device token. The debugging entity transmits an acknowledgement signal to the device after generation of the session key to initiate a debug session. The debugging entity transmits a debug unlock key to the device to cause the device to be unlocked for the debug session. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250004046A1

公开(公告)日：2025-01-02

申请号：US18882365

申请日：2024-09-11

Applicant: Intel Corporation

Inventor： Rakesh Kandula

IPC: G01R31/28

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to perform infield testing of a system in a package. An example die includes transmit circuits to communicate via respective communication channels and control circuitry to cause a first one of the transmit circuits to send a first pattern over a first one of the communication channels. Additionally, the example control circuitry is to cause second ones of the transmit circuits to respectively send a second pattern over second respective ones of the communication channels, the second pattern being at least one of an inverse of the first pattern or identical to the first pattern.

公开(公告)号：US20240103079A1

公开(公告)日：2024-03-28

申请号：US17954434

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Rakesh Kandula ,  Sankaran Menon ,  Rolf Kuehnis

IPC: G01R31/3185

CPC classification number: G01R31/318544

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to performing testing of a device while a system is operational. A device may include computing circuitry and host connectivity registers. Host connectivity registers contain configuration and memory mapping data programmed by system software upon power up of the device and computing system. The data contained in host connectivity registers should be always maintained while the computing system is operational. Scan test circuitry may be implemented, providing the ability to test the device while the system is operational. Preservation circuitry preserves or maintains the data stored in host connectivity registers allowing in-operation testing of the device, ensuring the device the ability to return to full operation at the end of in-operation testing without requiring system software to reprogram the host connectivity registers. By using scan-sealing methods and/or preserving the data in host connectivity registers during in-operation testing, performance and user experience are not degraded.

公开(公告)号：US20230408581A1

公开(公告)日：2023-12-21

申请号：US17841391

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Rakesh Kandula ,  Sankaran Menon ,  Seng Choon Thor ,  Shivaprashant Bulusu ,  Eswar Vadlamani ,  Ramakrishnan Venkatasubramanian

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318572

Abstract: Techniques for interface conversion and unicast for test content, firmware, and software delivery are described. An example apparatus comprises a scan test interface coupled to multiple circuits blocks to perform a scan test for the multiple circuit blocks, and circuitry coupled to input/output (IO) signals of the scan test interface to provide content for the multiple circuit blocks and to deliver a replicated content to multiple endpoints of the multiple circuit blocks (e.g., unicast technology). In another example, the circuitry is coupled to the IO signals of the scan test interface and a system/communication interface to decode packets received at the IO signals and convert the decoded packets to provide content through the system/communication interface for the multiple circuit blocks. Other examples are described and claimed.

公开(公告)号：US11257560B2

公开(公告)日：2022-02-22

申请号：US15717721

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Fei Su ,  Puneet Gupta ,  Wei Ming Lim ,  Terrence Huat Hin Tan ,  Amit Sanghani ,  Anubhav Sinha ,  Sudheer V Badana ,  Rakesh Kandula ,  Adithya B. S.

IPC: G11C29/12 ,  G11C29/48 ,  H01L23/538 ,  H03K17/56 ,  H03K17/00 ,  G11C29/50 ,  G11C29/02 ,  H01L25/065 ,  H01L23/00

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).