公开(公告)号：US20240220312A1

公开(公告)日：2024-07-04

申请号：US18091810

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Rakesh Kandula ,  Shlomo Avni ,  Fei Su

IPC: G06F9/48 ,  G06F11/263

CPC classification number: G06F9/4812 ,  G06F11/263

Abstract: Methods and apparatus relating to intelligent sensors for high quality silicon life cycle management as well as efficient infield structural and/or functional testing are described. In an embodiment, one or more registers store configuration data. A sensor having sensor event detection logic circuitry detects an event based at least in part on one or more sensor signals and the stored configuration data. The sensor event detection logic circuitry generates a signal to cause interrupt generator logic circuitry of the sensor to generate an interrupt. Other embodiments are also disclosed and claimed.

公开(公告)号：US09918088B2

公开(公告)日：2018-03-13

申请号：US14458524

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Qiang Li ,  Jumei Li ,  Yinglai Xi ,  Fei Su

IPC: H04N19/12 ,  H04N19/124 ,  H04N19/157 ,  H04N19/179 ,  H04N19/42 ,  H04N19/156 ,  H04N19/436

CPC classification number: H04N19/12 ,  H04N19/124 ,  H04N19/156 ,  H04N19/157 ,  H04N19/179 ,  H04N19/42 ,  H04N19/436

Abstract: A transform and inverse transform circuit is provided. The transform and inverse transform circuit includes: at least one quantization and inverse quantization circuit, including at least one quantization and inverse quantization unit, wherein each quantization and inverse quantization unit includes a plurality of first coefficients, and each quantization and inverse quantization unit performs quantization or inverse quantization on one of multiple ways of inputting data; and at least one one-dimensional transform circuit, coupled to the quantization and inverse quantization circuit, wherein the one-dimensional transform circuit includes a plurality of second coefficients, wherein the one-dimensional transform circuit performs one-dimensional transform on the inputting data processed by the quantization and inverse quantization circuit, wherein the plurality of first coefficients and the plurality of second coefficients are set up based on a video codec standard.

公开(公告)号：US20250052809A1

公开(公告)日：2025-02-13

申请号：US18233199

申请日：2023-08-11

Applicant: Intel Corporation

Inventor： Fei Su ,  Rakesh Kandula

IPC: G01R31/28 ,  G01R31/317

Abstract: Techniques and mechanisms for an integrated circuit (IC) die to support in-field testing and/or repair of a lane in a three-dimensional (3D) IC which is formed with multiple IC dies. In an embodiment, the 3D IC comprises test units which each correspond to a different partition comprising respective circuit resources. During in-field operation of the 3D IC, a given test unit is operable to detect both a first condition wherein two partitions are each in an idle state, and a second condition wherein a first link between the two partitions fails to satisfy a performance criteria. The idle states are indicated by a power management controller (PMC) agent during runtime operation of the 3D IC. In another embodiment, one or more test units configure an operational mode, based on the detected conditions, to substitute communication via the first lane with communication via a repair lane.

公开(公告)号：US20220365523A1

公开(公告)日：2022-11-17

申请号：US17747479

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Fei Su ,  Rita Chattopadhyay

IPC: G05B23/02 ,  G06K9/62

Abstract: Systems, apparatuses, and methods include technology that identifies a first dataset that comprises a plurality of data values, and partitions the first dataset into a plurality of bins to generate a second dataset, where the second dataset is a compressed version of the first dataset. The technology randomly subsamples data associated with the first dataset to obtain groups of randomly subsampled data, and generates a plurality of decision tree models during an unsupervised learning process based on the groups of randomly subsampled data and the second dataset.

公开(公告)号：US11257560B2

公开(公告)日：2022-02-22

申请号：US15717721

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Fei Su ,  Puneet Gupta ,  Wei Ming Lim ,  Terrence Huat Hin Tan ,  Amit Sanghani ,  Anubhav Sinha ,  Sudheer V Badana ,  Rakesh Kandula ,  Adithya B. S.

IPC: G11C29/12 ,  G11C29/48 ,  H01L23/538 ,  H03K17/56 ,  H03K17/00 ,  G11C29/50 ,  G11C29/02 ,  H01L25/065 ,  H01L23/00

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

公开(公告)号：US10929337B2

公开(公告)日：2021-02-23

申请号：US16422714

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Rahul Kundu ,  Fei Su ,  Prashant Goteti

IPC: G06F15/78 ,  G06F30/34 ,  G06F30/327 ,  G06F11/34 ,  G06F11/07 ,  G06F11/30

Abstract: Methods, systems and apparatuses may provide for technology that detects, by a first monitor in a first domain of a system, a presence of a first anomaly in the first domain and encodes, by the first monitor, the presence of the first anomaly and a weight of the first anomaly into a multi-level data structure. In one example, the technology also sends, by the first monitor, the multi-level data structure to a second monitor in a second domain of the system, wherein the second domain is located at a different hierarchical level in the system than the first domain.

公开(公告)号：US10685159B2

公开(公告)日：2020-06-16

申请号：US16020396

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Fei Su ,  Prashant Goteti

IPC: G06F11/00 ,  G06F30/367 ,  G01R31/3163 ,  G06N20/00 ,  G01R31/00 ,  G06F30/15

Abstract: In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.

公开(公告)号：US20190050515A1

公开(公告)日：2019-02-14

申请号：US16020396

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Fei Su ,  Prashant Goteti

IPC: G06F17/50 ,  G06N99/00 ,  G01R31/3163

Abstract: In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.