公开(公告)号：US20240030116A1

公开(公告)日：2024-01-25

申请号：US18375133

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/29

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20220230958A1

公开(公告)日：2022-07-21

申请号：US17716937

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Jiun Hann SIR ,  Poh Boon KHOO ,  Eng Huat GOH ,  Amruthavalli Pallavi ALUR ,  Debendra MALLIK

IPC: H01L23/522 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

公开(公告)号：US20220200183A1

公开(公告)日：2022-06-23

申请号：US17132921

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Srikant NEKKANTY ,  Debendra MALLIK ,  Joe F. WALCZYK ,  Saikumar JAYARAMAN ,  Feroz MOHAMMAD

IPC: H01R13/11 ,  H01R12/58 ,  H01L25/075 ,  H01L23/00 ,  H01L23/532

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

公开(公告)号：US20200286814A1

公开(公告)日：2020-09-10

申请号：US16291314

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Ravindranath MAHAJAN ,  Debendra MALLIK ,  Sujit SHARAN ,  Digvijay RAORANE

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/18 ,  H01L21/768 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US20200273784A1

公开(公告)日：2020-08-27

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20190287942A1

公开(公告)日：2019-09-19

申请号：US16349543

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Digvijay A. RAORANE ,  Ravindranath Vithal MAHAJAN ,  Mitul Bharat MODI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/48 ,  H01L21/768 ,  H01L21/822

Abstract: Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.

公开(公告)号：US20150221608A1

公开(公告)日：2015-08-06

申请号：US14686210

申请日：2015-04-14

Applicant: Intel Corporation

Inventor： Javier SOTO GONZALEZ ,  Charavana K. GURUMURTHY ,  Robert M. NICKERSON ,  Debendra MALLIK

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/20 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

Abstract translation: 微电子器件包括层叠安装基板，其包括裸片侧和具有设置在安装基板裸片侧的凹部中的表面光洁度层的平台侧。 导电的第一插头与表面光洁度层接触，并且导电的后续插头设置在安装衬底接地侧上，并且其电耦合到导电的第一插头并且直接设置在导电的第一插头的正下方。

公开(公告)号：US20240421073A1

公开(公告)日：2024-12-19

申请号：US18818285

申请日：2024-08-28

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20240128205A1

公开(公告)日：2024-04-18

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC: H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.