公开(公告)号：US20240061192A1

公开(公告)日：2024-02-22

申请号：US17889233

申请日：2022-08-16

申请人： Intel Corporation

发明人： Chia-Pin CHIU ,  Finian ROGERS ,  Tim Tri HOANG ,  Kaveh HOSSEINI ,  Omkar KARHADE

IPC分类号： G02B6/42

CPC分类号： G02B6/425 ,  G02B6/4243

摘要： Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a package substrate, a die coupled to the package substrate, a photonics integrated circuit (PIC) coupled to the die, and a fiber array unit (FAU) optically coupled to the PIC. In an embodiment, the FAU has a base with a first width and a protrusion with a second width that is smaller than the first width.

公开(公告)号：US20230314849A1

公开(公告)日：2023-10-05

申请号：US17710703

申请日：2022-03-31

申请人： Intel Corporation

发明人： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE ,  Tim Tri HOANG

IPC分类号： G02F1/01 ,  G02B6/293

CPC分类号： G02F1/0147 ,  G02B6/29395 ,  G02B6/2934 ,  G02F2203/15

摘要： Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, a micro-ring resonator (MRR) over the second substrate, a heater integrated into the MRR, a cladding over the MRR, an opening through the first substrate and the second substrate to expose a bottom surface of the MRR, and a base spanning across the opening.

公开(公告)号：US20220344247A1

公开(公告)日：2022-10-27

申请号：US17862300

申请日：2022-07-11

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

摘要： Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20220196935A1

公开(公告)日：2022-06-23

申请号：US17131682

申请日：2020-12-22

申请人： Intel Corporation

发明人： Xiaoqian LI ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Asako TODA ,  Divya PRATAP ,  Zhichao ZHANG

IPC分类号： G02B6/42

摘要： Embodiments disclosed herein include photonics packages. In an embodiment, a photonics package comprises a package substrate, and a compute die over the package substrate. In an embodiment, a photonics die is also over the package substrate, and the photonics die overhangs an edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the photonics die, and a fiber connector is coupled to the photonics die. In an embodiment, the fiber connector is attached to the IHS

公开(公告)号：US20240030116A1

公开(公告)日：2024-01-25

申请号：US18375133

申请日：2023-09-29

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/29

摘要： Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20230207479A1

公开(公告)日：2023-06-29

申请号：US17561547

申请日：2021-12-23

申请人： Intel Corporation

发明人： Omkar KARHADE ,  Nitin A. DESHPANDE

IPC分类号： H01L23/544 ,  H01L23/00

CPC分类号： H01L23/544 ,  H01L24/08 ,  H01L23/49816

摘要： Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

公开(公告)号：US20220415770A1

公开(公告)日：2022-12-29

申请号：US17356046

申请日：2021-06-23

申请人： Intel Corporation

发明人： Omkar KARHADE ,  Sai VADLAMANI ,  Xavier F. BRUN ,  Hemanth DHAVALESWARAPU

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/528 ,  H01L21/50 ,  H01L33/62 ,  H01L31/02

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20220196943A1

公开(公告)日：2022-06-23

申请号：US17131621

申请日：2020-12-22

申请人： Intel Corporation

发明人： Xiaoqian LI ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Ravindranath V. MAHAJAN

IPC分类号： G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367

摘要： A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

公开(公告)号：US20200273784A1

公开(公告)日：2020-08-27

申请号：US16646529

申请日：2017-12-30

申请人： Intel Corporation

发明人： Debendra MALLIK ,  Robert L. SANKMAN ,  Robert NICKERSON ,  Mitul MODI ,  Sanka GANESAN ,  Rajasekaran SWAMINATHAN ,  Omkar KARHADE ,  Shawna M. LIFF ,  Amruthavalli ALUR ,  Sri Chaitra J. CHAVALI

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

摘要： Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20230314704A1

公开(公告)日：2023-10-05

申请号：US17710709

申请日：2022-03-31

申请人： Intel Corporation

发明人： Chia-Pin CHIU ,  Kaveh HOSSEINI ,  Omkar KARHADE ,  Tim Tri HOANG

IPC分类号： G02B6/12 ,  H01L25/16

CPC分类号： G02B6/12007 ,  H01L25/167 ,  G02B6/29338

摘要： Embodiments disclosed herein include an optoelectronic system. In an embodiment, the optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and a temperature sensor is over the MRR in the cladding.