公开(公告)号：US20170127528A1

公开(公告)日：2017-05-04

申请号：US15336221

申请日：2016-10-27

Applicant: INKTEC CO., LTD.

Inventor： Kwang-Choon Chung ,  Byung Woong Moon

IPC: H05K3/10 ,  H05K1/02 ,  B41F11/00

CPC classification number: H05K3/106 ,  B41F11/00 ,  H05K1/028 ,  H05K3/0082 ,  H05K3/061 ,  H05K3/064 ,  H05K3/1275 ,  H05K2203/0143 ,  H05K2203/0369 ,  H05K2203/0557 ,  H05K2203/056 ,  H05K2203/107 ,  H05K2203/1545

Abstract: The present disclosure relates to an apparatus for manufacturing FPCB and method for manufacturing FPCB, having no limitations of length of a circuit pattern being formed on a base film.

公开(公告)号：US11317514B2

公开(公告)日：2022-04-26

申请号：US16484479

申请日：2018-02-09

Applicant: InkTec Co., Ltd.

Inventor： Kwang-Choon Chung ,  Byung Woong Moon ,  Su Han Kim ,  Jung Yoon Moon ,  Hyeon-Jun Seong ,  Jae Rin Kim

IPC: H05K3/06 ,  C09K13/00 ,  H05K1/09 ,  H05K1/11 ,  H05K3/18 ,  H05K3/28 ,  H05K3/42

Abstract: The present invention relates to a method for forming a circuit using a seed layer. The method for forming a circuit using a seed layer according to the present invention, may realize a fine pitch, increase the adhesion of the circuit, and prevent the migration phenomenon.

公开(公告)号：US11089691B2

公开(公告)日：2021-08-10

申请号：US16489361

申请日：2018-02-27

Applicant: InkTec Co., Ltd.

Inventor： Su Han Kim ,  Kwang-Choon Chung ,  Jung Yoon Moon ,  Sung In Ha ,  Byung Woong Moon

IPC: H05K3/06 ,  C09K13/00 ,  H05K3/24 ,  H05K3/12 ,  H05K3/18 ,  H05K3/38 ,  H05K3/10

Abstract: The disclosure relates to a microcircuit forming method. The microcircuit forming method according to the disclosure comprises: a seed-layer forming step for forming a high-reflectivity seed layer on a substrate material by using a conductive material; a pattern-layer forming step for forming a pattern layer on the seed layer, the pattern layer having a pattern hole arranged thereon to allow the seed layer to be selectively exposed therethrough; a plating step for filling the pattern hole with a conductive material; a pattern-layer removing step for removing the pattern layer; and a seed-layer patterning step for removing a part of the seed layer which does not overlap the conductive material in the plating step, wherein the high-reflectivity seed layer has a specular reflection property.

公开(公告)号：US10887997B2

公开(公告)日：2021-01-05

申请号：US15336221

申请日：2016-10-27

Applicant: INKTEC CO., LTD.

Inventor： Kwang-Choon Chung ,  Byung Woong Moon

IPC: H05K3/10 ,  H05K3/12 ,  H05K3/06 ,  H05K3/00 ,  B41F11/00

Abstract: The present disclosure relates to an apparatus for manufacturing flexible printed circuit board (FPCB) and method for manufacturing the FPCB, having no limitations of length of a circuit pattern being formed on a base film.

公开(公告)号：US10383212B2

公开(公告)日：2019-08-13

申请号：US16025641

申请日：2018-07-02

Applicant: INKTEC CO., LTD.

Inventor： Kwang-Choon Chung ,  Byung Woong Moon

IPC: H05K9/00 ,  H05K1/02 ,  H01R12/79 ,  H05K1/11 ,  H01B7/08 ,  H05K3/42

Abstract: The present disclosure relates a printed circuit board having an EMI shielding function. In an example embodiment, the printed circuit board includes a substrate, a signal unit disposed on the substrate, a ground unit disposed in parallel with the signal unit, an insulation layer disposed above the substrate and covering the signal unit and the ground unit, an EMI shielding layer disposed on the insulation layer and under the substrate, respectively, and a shielding bridge passing through the substrate and the insulation layer at opposite sides of the signal unit and electrically connecting the EMI shielding layer disposed on the insulation layer to the EMI shielding layer disposed under the substrate.

公开(公告)号：US11453823B2

公开(公告)日：2022-09-27

申请号：US16487104

申请日：2018-02-20

Applicant: InkTec Co., Ltd.

Inventor： Kwang-Choon Chung ,  Byung Woong Moon ,  Su Han Kim ,  Jae Rin Kim

IPC: C09K13/00 ,  C23F1/00 ,  C25D3/38 ,  C25D5/02 ,  H05K1/09 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46 ,  C25D5/10

Abstract: The disclosure relates to a method for manufacturing a transfer film including an electrode layer, the method comprising: an electrode layer formation step of forming an electrode layer on a carrier member by using a conductive material; a placement step of placing the carrier member on at least one side of an insulating resin layer respectively; a bonding step of bonding the carrier member and the insulating resin layer together by applying pressure thereto; and a transfer step of removing the carrier member to transfer the electrode layer on the insulating resin layer.

公开(公告)号：US11160171B2

公开(公告)日：2021-10-26

申请号：US16485174

申请日：2018-02-14

Applicant: InkTec Co., Ltd.

Inventor： Kwang-Choon Chung ,  Su Han Kim ,  Jung Yoon Moon ,  Hyeon-Jun Seong ,  Byung Woong Moon

IPC: H05K3/06 ,  C09K13/06 ,  C23F1/30

Abstract: The present invention relates to an etching solution composition for selectively etching only silver, a silver alloy, or a silver compound, and to a circuit forming method using the composition. The circuit forming method according to the present invention is characterized in that, in a substrate material in which an electrically conductive seed layer and a circuit layer are formed of heterogeneous metals, only the seed layer is selectively etched to enable the implementation of fine pitches. In addition, the present invention relates to a circuit forming method and an etching solution composition, wherein only a seed layer of silver (Ag), a silver alloy, or a silver compound is selectively etched without etching a copper (Cu) plated circuit.