公开(公告)号：US11600615B2

公开(公告)日：2023-03-07

申请号：US16919833

申请日：2020-07-02

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Adriaan Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66 ,  H01L29/74 ,  H01L29/732

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US11757281B2

公开(公告)日：2023-09-12

申请号：US17544448

申请日：2021-12-07

Applicant: Infineon Technologies AG

Inventor： Anton Gutsul ,  Joost Adriaan Willemen

IPC: H02H9/04 ,  H01R13/713 ,  H01R13/66

CPC classification number: H02H9/042 ,  H02H9/045 ,  H01R13/6666 ,  H01R13/713

Abstract: An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.

公开(公告)号：US20230080466A1

公开(公告)日：2023-03-16

申请号：US17941684

申请日：2022-09-09

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Vadim Valentinovic Vendt ,  Joost Adriaan Willemen

IPC: H01L27/02 ,  H02H9/04

Abstract: A semiconductor device includes a semiconductor body, first and second contact pads disposed on an upper surface of the semiconductor body, a lateral ESD protection device formed in the semiconductor body, and a vertical ESD protection device formed in the semiconductor body, wherein the lateral ESD protection device and the vertical ESD protection device together form a unidirectional device between the first and second contact pads, and wherein the lateral ESD protection device is formed in a first portion of the semiconductor body that is laterally electrically isolated from a vertical current path of the vertical ESD protection device.

公开(公告)号：US20200335494A1

公开(公告)日：2020-10-22

申请号：US16919833

申请日：2020-07-02

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Adriaan Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US20240204516A1

公开(公告)日：2024-06-20

申请号：US18591681

申请日：2024-02-29

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0288

Abstract: An overvoltage protection device includes a semiconductor die, first and second semiconductor devices that are monolithically integrated in the semiconductor die and arranged in an anti-serial configuration with a conductive link connected between the first and second semiconductor devices at a central node of the overvoltage protection device, the first and second semiconductor devices each being two terminal semiconductor devices with one way conduction characteristics, a first conductive electrode connected to a terminal of the first semiconductor device that is opposite from the central node, a second conductive electrode connected to a terminal of the second semiconductor device that is opposite from the central node, a monolithically integrated feature of the semiconductor die that compensates for a parasitic capacitance of the overvoltage protection device such that the capacitances of the overvoltage protection device under operation are substantially symmetrical with respect to the central node.

公开(公告)号：US20230395656A1

公开(公告)日：2023-12-07

申请号：US18234992

申请日：2023-08-17

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Joost Adriaan Willemen

IPC: H01L29/06 ,  H01L29/735 ,  H01L29/74 ,  H01L29/861 ,  H01L29/868

CPC classification number: H01L29/0649 ,  H01L29/0692 ,  H01L29/868 ,  H01L29/7436 ,  H01L29/8611 ,  H01L29/735

Abstract: An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

公开(公告)号：US11764205B2

公开(公告)日：2023-09-19

申请号：US17348291

申请日：2021-06-15

Applicant: Infineon Technologies AG

Inventor： Joost Adriaan Willemen

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861 ,  H01L27/08

CPC classification number: H01L27/0248 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/8618

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

公开(公告)号：US11069674B2

公开(公告)日：2021-07-20

申请号：US16538182

申请日：2019-08-12

Applicant: Infineon Technologies AG

Inventor： Joost Adriaan Willemen

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861 ,  H01L27/08

Abstract: A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient mi. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m2. The junction grading coefficients m1, m2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

公开(公告)号：US11929305B2

公开(公告)日：2024-03-12

申请号：US17532446

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Klaus Diefenbeck ,  Joost Adriaan Willemen

IPC: H01L23/48 ,  H01L21/822 ,  H01L23/482 ,  H01L27/02 ,  H01L21/56

CPC classification number: H01L23/4825 ,  H01L21/822 ,  H01L27/0292 ,  H01L21/56 ,  H01L27/0255

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

公开(公告)号：US11821944B2

公开(公告)日：2023-11-21

申请号：US17680551

申请日：2022-02-25

Applicant: Infineon Technologies AG

Inventor： Josef-Paul Schaffer ,  Joost Adriaan Willemen

IPC: G01R31/02 ,  G01R31/26 ,  G01R31/30 ,  G01R31/319 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/3004 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/31924 ,  H01L22/34 ,  H01L2924/00 ,  H01L2924/0002

Abstract: An apparatus for measuring a device current of a device under test (DUT) includes a first circuit including a first terminal for coupling to a first connection terminal of the DUT. The first circuit is configured to supply a first test voltage for the first terminal and to output a first output voltage sensed at the first terminal. The apparatus further includes a second circuit having a second terminal for coupling to a second connection terminal of the DUT. The second circuit is configured to supply a second test voltage for the second terminal and to output a second output voltage sensed at the second terminal. The apparatus further includes a third circuit configured to determine the device current of the DUT based on the first output voltage, the second output voltage, the first test voltage and the second test voltage. The first circuit and the second circuit are identical.