公开(公告)号：US11600615B2

公开(公告)日：2023-03-07

申请号：US16919833

申请日：2020-07-02

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Adriaan Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66 ,  H01L29/74 ,  H01L29/732

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US20160300827A1

公开(公告)日：2016-10-13

申请号：US14817928

申请日：2015-08-04

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/737 ,  H01L21/8224 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.

Abstract translation: 半导体器件包括具有晶闸管和设置在衬底中的横向触发元件的垂直保护器件。 横向触发元件用于触发垂直保护装置。

公开(公告)号：US12009361B2

公开(公告)日：2024-06-11

申请号：US18100043

申请日：2023-01-23

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/66 ,  H01L29/732 ,  H01L29/74 ,  H01L29/861

CPC classification number: H01L27/067 ,  H01L27/0262 ,  H01L29/6609 ,  H01L29/861 ,  H01L29/66371 ,  H01L29/732 ,  H01L29/7404

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US10672758B2

公开(公告)日：2020-06-02

申请号：US15787124

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Stefan Pompl ,  Andre Schmenn ,  Joost Willemen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/87 ,  H01L29/74

Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

公开(公告)号：US20230080466A1

公开(公告)日：2023-03-16

申请号：US17941684

申请日：2022-09-09

Applicant: Infineon Technologies AG

Inventor： Egle Tylaite ,  Vadim Valentinovic Vendt ,  Joost Adriaan Willemen

IPC: H01L27/02 ,  H02H9/04

Abstract: A semiconductor device includes a semiconductor body, first and second contact pads disposed on an upper surface of the semiconductor body, a lateral ESD protection device formed in the semiconductor body, and a vertical ESD protection device formed in the semiconductor body, wherein the lateral ESD protection device and the vertical ESD protection device together form a unidirectional device between the first and second contact pads, and wherein the lateral ESD protection device is formed in a first portion of the semiconductor body that is laterally electrically isolated from a vertical current path of the vertical ESD protection device.

公开(公告)号：US20200335494A1

公开(公告)日：2020-10-22

申请号：US16919833

申请日：2020-07-02

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Adriaan Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US10741548B2

公开(公告)日：2020-08-11

申请号：US14817928

申请日：2015-08-04

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66 ,  H01L29/74 ,  H01L29/732

Abstract: A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.

公开(公告)号：US20240088130A1

公开(公告)日：2024-03-14

申请号：US17941901

申请日：2022-09-09

Applicant: Infineon Technologies AG

Inventor： Benedikt Kindl ,  Juliane Laurer ,  Max Stelzer ,  Vadim Valentinovic Vendt

IPC: H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0248 ,  H01L23/528 ,  H01L23/5226

Abstract: A semiconductor device includes a semiconductor body having an upper surface, a group of first upper-level metal fingers and second upper-level metal fingers that are arranged alternatingly with one another, wherein each of the first upper-level metal fingers is electrically connected to the semiconductor body by the first lower-level conductive fingers, wherein each of the second upper-level metal fingers is electrically connected to the semiconductor body by the second lower-level conductive fingers, wherein the group of first lower-level conductive fingers and second lower-level conductive fingers defines a connection area over the upper surface, and wherein in the connection area the first upper-level metal fingers are at least partially non-overlapping with the second upper-level metal fingers.

公开(公告)号：US20230163123A1

公开(公告)日：2023-05-25

申请号：US18100043

申请日：2023-01-23

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L27/067 ,  H01L27/0262 ,  H01L29/861 ,  H01L29/6609 ,  H01L29/7404

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US20180108648A1

公开(公告)日：2018-04-19

申请号：US15787124

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Stefan Pompl ,  Andre Schmenn ,  Joost Willemen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.