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公开(公告)号：US12107119B2
公开(公告)日：2024-10-01
申请号：US17479522
申请日：2021-09-20
CPC分类号： H01L29/045 , H01L27/0617 , H01L29/2003
摘要： A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.
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公开(公告)号：US20230090017A1
公开(公告)日：2023-03-23
申请号：US17479522
申请日：2021-09-20
摘要： A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.
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公开(公告)号：US10476016B2
公开(公告)日：2019-11-12
申请号：US16138934
申请日：2018-09-21
IPC分类号： H01L21/28 , G06N3/063 , H01L51/00 , G11C11/54 , H01L29/08 , H01L51/05 , H01L21/8238 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/778 , H01L29/12 , H01L29/10 , H01L29/06 , H01L29/43 , H01L29/51 , H01L29/423 , H01L29/788
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
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公开(公告)号：US10115916B2
公开(公告)日：2018-10-30
申请号：US14684346
申请日：2015-04-11
IPC分类号： H01L51/05 , G06N3/063 , H01L29/08 , H01L29/51 , H01L21/8238 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/778 , G11C11/54 , H01L29/12 , H01L29/10 , H01L29/43 , H01L51/00 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/06
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
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公开(公告)号：US09735383B2
公开(公告)日：2017-08-15
申请号：US15262145
申请日：2016-09-12
IPC分类号： H01L29/06 , H01L31/00 , H01L51/05 , H01L21/8238 , H01L29/08 , H01L29/165 , H01L29/267 , H01L29/66 , H01L29/778 , G06N3/063 , G11C11/54 , H01L29/12 , H01L29/10 , H01L29/43 , H01L29/51 , H01L51/00 , H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L51/0566 , G06N3/063 , G06N3/0635 , G11C11/54 , H01L21/28273 , H01L21/8238 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1054 , H01L29/122 , H01L29/125 , H01L29/127 , H01L29/165 , H01L29/267 , H01L29/42324 , H01L29/432 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7783 , H01L29/7786 , H01L29/7788 , H01L29/7881 , H01L51/0055 , H01L51/0541 , H01L51/0545 , H01L51/0562 , H01L2251/301
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
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公开(公告)号：US20170005281A1
公开(公告)日：2017-01-05
申请号：US15262145
申请日：2016-09-12
IPC分类号： H01L51/05 , H01L29/43 , G06N3/063 , H01L29/08 , H01L29/12 , G11C11/54 , H01L29/10 , H01L29/51
CPC分类号： H01L51/0566 , G06N3/063 , G06N3/0635 , G11C11/54 , H01L21/28273 , H01L21/8238 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1054 , H01L29/122 , H01L29/125 , H01L29/127 , H01L29/165 , H01L29/267 , H01L29/42324 , H01L29/432 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7783 , H01L29/7786 , H01L29/7788 , H01L29/7881 , H01L51/0055 , H01L51/0541 , H01L51/0545 , H01L51/0562 , H01L2251/301
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
摘要翻译： 基于捕获和去除捕获空穴或电子和/或两种载体的复合的装置结构通过在接近界面深双极态或量子阱/点中的载流子捕获来获得，其用作半导体层中的双极阱，或者 在栅介质/阻挡层中。 在任一情况下，捕获的势垒很小，并且通过在深陷阱状态和/或量子阱/点中的载流子限制提供保留。 设备架构可用作三个终端或两个终端设备。
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公开(公告)号：US20160035989A1
公开(公告)日：2016-02-04
申请号：US14884744
申请日：2015-10-15
CPC分类号： H01L51/0508 , H01L27/1222 , H01L27/1251 , H01L27/286 , H01L27/3244 , H01L27/326 , H01L27/3274 , H01L29/1066 , H01L29/267 , H01L29/66742 , H01L29/66916 , H01L29/808 , H01L51/002 , H01L51/0021 , H01L2227/323
摘要： Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
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公开(公告)号：US09166181B2
公开(公告)日：2015-10-20
申请号：US14184488
申请日：2014-02-19
CPC分类号： H01L51/0508 , H01L27/1222 , H01L27/1251 , H01L27/286 , H01L27/3244 , H01L27/326 , H01L27/3274 , H01L29/1066 , H01L29/267 , H01L29/66742 , H01L29/66916 , H01L29/808 , H01L51/002 , H01L51/0021 , H01L2227/323
摘要： Junction field-effect transistors including inorganic channels and organic gate junctions are used in some applications for forming high resolution active matrix displays. Arrays of such junction field-effect transistors are electrically connected to thin film switching transistors and provide high drive currents for passive devices such as organic light emitting diodes.
摘要翻译： 包括无机通道和有机栅极结在内的结场场效应晶体管用于形成高分辨率有源矩阵显示器的一些应用中。 这种结型场效应晶体管的阵列电连接到薄膜开关晶体管，并为无源器件（例如有机发光二极管）提供高驱动电流。
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公开(公告)号：US20150235123A1
公开(公告)日：2015-08-20
申请号：US14684346
申请日：2015-04-11
CPC分类号： H01L51/0566 , G06N3/063 , G06N3/0635 , G11C11/54 , H01L21/28273 , H01L21/8238 , H01L29/0649 , H01L29/0665 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1054 , H01L29/122 , H01L29/125 , H01L29/127 , H01L29/165 , H01L29/267 , H01L29/42324 , H01L29/432 , H01L29/51 , H01L29/66431 , H01L29/66462 , H01L29/66477 , H01L29/7783 , H01L29/7786 , H01L29/7788 , H01L29/7881 , H01L51/0055 , H01L51/0541 , H01L51/0545 , H01L51/0562 , H01L2251/301
摘要： Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
摘要翻译： 基于捕获和去除捕获空穴或电子和/或两种载体的复合的装置结构通过在接近界面深双极态或量子阱/点中的载流子捕获来获得，其用作半导体层中的双极阱，或者 在栅介质/阻挡层中。 在任一情况下，捕获的势垒很小，并且通过在深陷阱状态和/或量子阱/点中的载流子限制提供保留。 设备架构可用作三个终端或两个终端设备。
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公开(公告)号：US09041079B1
公开(公告)日：2015-05-26
申请号：US14312467
申请日：2014-06-23
CPC分类号： G11C13/047 , G11C11/54 , G11C13/0014 , G11C13/0016 , G11C2213/53 , H01L27/1443 , H01L27/307 , H01L51/0071
摘要： An optoelectronic device may include an insulating substrate, a semiconductor channel region located on the insulating substrate, and a source region and a drain region in contact with the semiconductor channel region. A photoswitchable material may be located on the semiconductor channel region between the source region and the drain region, such that the photoswitchable material includes a first structural state based on being exposed to a first optical wavelength, and includes a second structural state based on being exposed to a second optical wavelength. The first structural state causes a first electrical current to flow between the source region and the drain region, while the second structural state causes a second electrical current to flow between the source region and the drain region.
摘要翻译： 光电子器件可以包括绝缘衬底，位于绝缘衬底上的半导体沟道区，以及与半导体沟道区接触的源区和漏区。 光可切换材料可以位于源极区域和漏极区域之间的半导体沟道区域上，使得可照光开关材料基于暴露于第一光学波长包括第一结构状态，并且包括基于暴露的第二结构状态 到第二光波长。 第一结构状态引起第一电流在源极区域和漏极区域之间流动，而第二结构状态引起第二电流在源极区域和漏极区域之间流动。
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