公开(公告)号：US20150214332A1

公开(公告)日：2015-07-30

申请号：US14426690

申请日：2012-11-13

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Lingkuan Meng ,  Xiaobin He ,  Guanglu Chen ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/51 ,  H01L29/66492 ,  H01L29/66621 ,  H01L29/66833

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract translation: 一种用于制造虚拟栅极结构的方法。 该方法可以包括：顺序地在半导体衬底上形成伪栅极氧化物层和虚拟栅极材料层; 在虚拟栅极材料层上形成ONO结构; 在ONO结构上形成顶部非晶硅层; 在顶部非晶硅层上形成图案化的光致抗蚀剂层; 用图案化的光致抗蚀剂层作为掩模蚀刻顶部非晶硅层，蚀刻停止在ONO结构上; 用图案化的光致抗蚀剂层和顶部非晶硅层的剩余部分作为掩模蚀刻ONO结构，蚀刻停止在虚拟栅极材料层上; 去除图案化的光致抗蚀剂层; 并且蚀刻伪栅极材料层，蚀刻停止在虚设栅极氧化层处以形成虚拟栅极结构。

公开(公告)号：US10157956B2

公开(公告)日：2018-12-18

申请号：US15477191

申请日：2017-04-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Hushan Cui ,  Jinjuan Xiang ,  Xiaobin He ,  Tao Yang ,  Junfeng Li ,  Chao Zhao

IPC: H01L21/00 ,  H01L27/146 ,  H01L31/0216 ,  H01L31/0232

Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m≥1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

公开(公告)号：US09911617B2

公开(公告)日：2018-03-06

申请号：US15299169

申请日：2016-10-20

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Junjie Li ,  Junfeng Li ,  Qinghua Yang ,  Jinbiao Liu ,  Xiaobin He

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/32136 ,  H01L21/32139

Abstract: The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.

公开(公告)号：US09331172B2

公开(公告)日：2016-05-03

申请号：US14426690

申请日：2012-11-13

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Lingkuan Meng ,  Xiaobin He ,  Guanglu Chen ,  Chao Zhao

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31055 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/51 ,  H01L29/66492 ,  H01L29/66621 ,  H01L29/66833

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract translation: 一种用于制造虚拟栅极结构的方法。 该方法可以包括：顺序地在半导体衬底上形成伪栅极氧化物层和虚拟栅极材料层; 在虚拟栅极材料层上形成ONO结构; 在ONO结构上形成顶部非晶硅层; 在顶部非晶硅层上形成图案化的光致抗蚀剂层; 用图案化的光致抗蚀剂层作为掩模蚀刻顶部非晶硅层，蚀刻停止在ONO结构上; 用图案化的光致抗蚀剂层和顶部非晶硅层的剩余部分作为掩模蚀刻ONO结构，蚀刻停止在虚拟栅极材料层上; 去除图案化的光致抗蚀剂层; 并且蚀刻伪栅极材料层，蚀刻停止在虚设栅极氧化层处以形成虚拟栅极结构。