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公开(公告)号：US11086796B2
公开(公告)日：2021-08-10
申请号：US16422911
申请日：2019-05-24
发明人： Berndt Gammel , Gerd Dirscherl , Bernd Meyer , Steffen Sonnekalb
摘要： A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.
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公开(公告)号：US10514892B2
公开(公告)日：2019-12-24
申请号：US13951635
申请日：2013-07-26
发明人： Berndt Gammel , Stefan Mangard , Steffen Sonnekalb
摘要： An apparatus for detecting integrity violation includes a feedback shift register including a plurality of registers connected in series, and a feedback function unit connected between an output of a number of the registers and an input of at least one of the registers. The apparatus further includes an integrity violation detector adapted to determine as to whether a sequence of values at an input or output of at least one of the registers, or a logic combination thereof, is a non-constant sequence or a constant sequence. The apparatus is further adapted to output an indication that the feedback shift register is in an integral state if the sequence of values is a non-constant sequence, or to output an indication that the feedback shift register is subjected to an integrity violation if the sequence of values is a constant sequence.
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3.发明申请公开(公告)号：US20190243789A1
公开(公告)日：2019-08-08
申请号：US16258710
申请日：2019-01-28
发明人： Gerd Dirscherl , Benedikt Driessen , Gunther Fenzl , Franz Klug , Bernd Meyer , Steffen Sonnekalb
IPC分类号： G06F13/20
CPC分类号： G06F13/20 , G06F2213/40
摘要： A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.
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4.发明申请Apparatus Comprising a Pair of an Alarm Condition Generator and an Associated Alarm Circuit, Chip Card, and Method 有权包括一对报警条件发生器和相关报警电路，芯片卡和方法的装置公开(公告)号：US20140306823A1
公开(公告)日：2014-10-16
申请号：US13862882
申请日：2013-04-15
发明人： Steffen Sonnekalb , Stefan Mangard
IPC分类号： G08B23/00
CPC分类号： G08B23/00 , G06F11/2284 , G06F11/27 , G08B29/12 , G08B29/18
摘要： An apparatus includes a pair of an alarm condition generator and an associated alarm circuit and a test circuit. The alarm circuit is configured to generate an alarm signal in response to a detection of an associated alarm condition. The alarm condition generator is configured to generate the associated alarm condition for its associated alarm circuit in response to a reception of a first reset of a first type of reset. The test circuit is configured to receive the alarm signal and the first reset and to generate in response to a reception of both the first reset and the alarm signal a second reset of a second type of reset.
摘要翻译： 一种装置包括一对报警条件发生器和相关联的报警电路和测试电路。 报警电路被配置为响应于相关警报状况的检测而产生报警信号。 报警条件发生器被配置为响应于接收到第一类型的复位的第一复位而为其相关联的报警电路产生相关联的报警条件。 测试电路被配置为接收报警信号和第一复位，并响应于第一复位和报警信号两者的接收产生第二类型复位的第二复位。
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公开(公告)号：US20220261176A1
公开(公告)日：2022-08-18
申请号：US17666762
申请日：2022-02-08
发明人： Steffen Sonnekalb
IPC分类号： G06F3/06
摘要： A storage device comprises a plurality of bitwise-modifiable memory cells. A control device is also provided, which, in order to modify existing data content written to a group of memory cells with new data content to be written, is designed to compare the existing data content and the data content to be written in order to obtain a comparison result. The control device is designed to determine a subset of the group of memory cells for modification and a remaining length based on the comparison result, and to write the data content to be written to the subset, leaving the remaining set at least partially unchanged. For modifying the existing data content, the storage device is designed to read from a memory location of the storage device and to verify the correctness of the memory location.
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公开(公告)号：US20190114111A1
公开(公告)日：2019-04-18
申请号：US16156046
申请日：2018-10-10
发明人： Joel Hatsch , Bernd Meyer , Jan Otterstedt , Steffen Sonnekalb
摘要： A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.
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公开(公告)号：US20150215129A1
公开(公告)日：2015-07-30
申请号：US14604187
申请日：2015-01-23
发明人： Steffen Sonnekalb
CPC分类号： H04L9/3228 , G06F12/1408 , G09C1/00 , H04L9/0861 , H04L9/0894
摘要： A method for encrypting data stored in a memory area is proposed, wherein the data are encrypted on the basis of a key identification for the data and on the basis of a one-time key.
摘要翻译： 提出了一种对存储在存储器区域中的数据进行加密的方法，其中基于数据的密钥标识和一次性密钥对数据进行加密。
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公开(公告)号：US12079507B2
公开(公告)日：2024-09-03
申请号：US17666762
申请日：2022-02-08
发明人： Steffen Sonnekalb
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0673
摘要： A storage device comprises a plurality of bitwise-modifiable memory cells. A control device is also provided, which, in order to modify existing data content written to a group of memory cells with new data content to be written, is designed to compare the existing data content and the data content to be written in order to obtain a comparison result. The control device is designed to determine a subset of the group of memory cells for modification and a remaining length based on the comparison result, and to write the data content to be written to the subset, leaving the remaining set at least partially unchanged. For modifying the existing data content, the storage device is designed to read from a memory location of the storage device and to verify the correctness of the memory location.
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公开(公告)号：US12038808B2
公开(公告)日：2024-07-16
申请号：US18305497
申请日：2023-04-24
发明人： Steffen Sonnekalb
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F11/1004
摘要： A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.
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公开(公告)号：US20230367912A1
公开(公告)日：2023-11-16
申请号：US18311981
申请日：2023-05-04
发明人： Marcus Janke , Steffen Sonnekalb
摘要： A semiconductor chip apparatus including a memory having a plurality of memory locations, a memory access element, and an integrity check device configured to store a reference value for a check function over values stored in the memory locations and, in a case of write access to a memory location, configured to update a check value with the value to be written by the write access if the check value represents the value stored in the memory location prior to the write access, and configured to compare the reference value with the check value after the check value has been generated and output a signal depending on a result of the comparison.
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