公开(公告)号：US12190224B2

公开(公告)日：2025-01-07

申请号：US17136744

申请日：2020-12-29

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yao-Hua Chen ,  Yu-Xiang Yen ,  Wan-Shan Hsieh ,  Chih-Tsun Huang ,  Juin-Ming Lu ,  Jing-Jia Liou

IPC: G06F15/80 ,  G06F9/48 ,  G06N3/049 ,  G06N3/063 ,  G06F9/50

Abstract: A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.

公开(公告)号：US11657273B2

公开(公告)日：2023-05-23

申请号：US16728341

申请日：2019-12-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yao-Hua Chen ,  Jing-Jia Liou ,  Chih-Tsun Huang ,  Juin-Ming Lu

IPC: G06N3/08 ,  G06N3/049 ,  G06N3/044

CPC classification number: G06N3/08 ,  G06N3/044 ,  G06N3/049

Abstract: An adaptive learning power modeling method includes: sampling at least one of a plurality of network components to form a power consumption evaluation network according to at least one parameter within a parameter range; evaluating a predictive power consumption of a to-be-measured circuit by the power consumption evaluation network; training and evaluating an actual power consumption and the predictive power consumption of the to-be-measured circuit by the power consumption evaluation network to obtain an evaluation result; and performing training according to the evaluation result to determine whether to change the power consumption evaluation network.

公开(公告)号：US20240152731A1

公开(公告)日：2024-05-09

申请号：US18349982

申请日：2023-07-11

Applicant: Industrial Technology Research Institute

Inventor： Yao-Hua Chen ,  Jiun-Kai Yang ,  Chih-Tsun Huang

IPC: G06N3/045

CPC classification number: G06N3/045

Abstract: A hardware-aware zero-cost neural network architecture search system is configured to perform the following. A neural network search space is divided into multiple search blocks. Each of the search blocks includes multiple candidate blocks. The candidate blocks are guided and scored through a latent pattern generator. The candidate blocks in each of the search blocks are scored through a zero-cost accuracy proxy. One of the candidate blocks included in each of the search blocks is sequentially selected as selected candidate blocks, the selected candidate blocks are combined into multiple neural networks to be evaluated, and network potential of the neural networks to be evaluated is calculated according to scores of the selected candidate blocks. One neural network to be evaluated with the highest network potential is selected to determine the corresponding selected candidate blocks.

公开(公告)号：US20180074702A1

公开(公告)日：2018-03-15

申请号：US15391082

申请日：2016-12-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yao-Hua Chen ,  Che-Wei Hsu ,  Juin-Ming Lu ,  Wei-Shiang Lin ,  Jing-Jia Liou ,  Chih-Tsun Huang

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0215 ,  G06F12/0607 ,  G11C7/22

Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.

公开(公告)号：US11551066B2

公开(公告)日：2023-01-10

申请号：US16248042

申请日：2019-01-15

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yao-Hua Chen ,  Chun-Chen Chen ,  Chih-Tsun Huang ,  Jing-Jia Liou ,  Chun-Hung Lai ,  Juin-Ming Lu

IPC: G06F3/06 ,  G06N3/063 ,  G06F13/42 ,  G06F9/30

Abstract: A DNN hardware accelerator and an operation method of the DNN hardware accelerator are provided. The DNN hardware accelerator includes: a network distributor for receiving an input data and distributing respective bandwidth of a plurality of data types of a target data amount based on a plurality of bandwidth ratios of the target data amount; and a processing element array coupled to the network distributor, for communicating data of the data types of the target data amount between the network distributor based on the distributed bandwidth of the data types.

公开(公告)号：US10365829B2

公开(公告)日：2019-07-30

申请号：US15391082

申请日：2016-12-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yao-Hua Chen ,  Che-Wei Hsu ,  Juin-Ming Lu ,  Wei-Shiang Lin ,  Jing-Jia Liou ,  Chih-Tsun Huang

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C7/22

Abstract: A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.