公开(公告)号：US12190224B2

公开(公告)日：2025-01-07

申请号：US17136744

申请日：2020-12-29

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Yao-Hua Chen ,  Yu-Xiang Yen ,  Wan-Shan Hsieh ,  Chih-Tsun Huang ,  Juin-Ming Lu ,  Jing-Jia Liou

IPC: G06F15/80 ,  G06F9/48 ,  G06N3/049 ,  G06N3/063 ,  G06F9/50

Abstract: A processing element architecture adapted to a convolution comprises a plurality of processing elements and a delayed queue circuit. The plurality of processing elements includes a first processing element and a second processing element, wherein the first processing element and the second processing element perform the convolution according to a shared datum at least. The delayed queue circuit connects to the first processing element and connects to the second processing element. The delayed queue circuit receives the shared datum sent by the first processing element, and sends the shared datum to the second processing element after receiving the shared datum and waiting for a time interval.