Invention Grant
- Patent Title: Memory transaction-level modeling method and system
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Application No.: US15391082Application Date: 2016-12-27
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Publication No.: US10365829B2Publication Date: 2019-07-30
- Inventor: Yao-Hua Chen , Che-Wei Hsu , Juin-Ming Lu , Wei-Shiang Lin , Jing-Jia Liou , Chih-Tsun Huang
- Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Applicant Address: TW Chutung, Hsinchu
- Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee Address: TW Chutung, Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: TW105129513A 20160910
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F3/06 ; G06F12/02 ; G06F12/06 ; G11C7/22

Abstract:
A memory transaction-level modeling method and a memory transaction-level modeling system are provided. The memory transaction-level modeling method is used for simulating the operation of outputting at least one command to the memory. The memory includes a plurality of banks each of which corresponds with a bank status table. The memory transaction-level modeling method includes the following steps: An event is received. Whether one of the bank status tables is needed to be updated is determined. If one of the bank status tables is needed to be updated, this bank status table is recovered according to a TMP queue. A command is outputted to the memory according to a command queue. The outputted command is stored in the TMP queue. Some of the bank status tables are updated and others of the bank status tables are kept unchanged.
Public/Granted literature
- US20180074702A1 MEMORY TRANSACTION-LEVEL MODELING METHOD AND SYSTEM Public/Granted day:2018-03-15
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