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    Semiconductor memory device
    1.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20090219775A1

    公开(公告)日：2009-09-03

    申请号：US12154870

    申请日：2008-05-28

    申请人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    发明人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/12 ,  G11C11/401

    摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

    摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08225150B2

    公开(公告)日：2012-07-17

    申请号：US13149683

    申请日：2011-05-31

    申请人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    发明人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    IPC分类号： G11C29/00 ,  G01R31/28 ,  H03M13/00

    CPC分类号： G11C29/12 ,  G11C11/401

    摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

    摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20110231717A1

    公开(公告)日：2011-09-22

    申请号：US13149683

    申请日：2011-05-31

    申请人： Hwang HUR ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    发明人： Hwang HUR ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    IPC分类号： G11C29/04 ,  G06F11/22

    CPC分类号： G11C29/12 ,  G11C11/401

    摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

    摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元来执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07979758B2

    公开(公告)日：2011-07-12

    申请号：US12154870

    申请日：2008-05-28

    申请人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    发明人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

    IPC分类号： G11C29/00 ,  G01R31/28

    CPC分类号： G11C29/12 ,  G11C11/401

    摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

    摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

    Analog delay locked loop having duty cycle correction circuit
    5.
    发明授权
    Analog delay locked loop having duty cycle correction circuit 失效
    具有占空比校正电路的模拟延迟锁定环

    公开(公告)号：US07078949B2

    公开(公告)日：2006-07-18

    申请号：US10750243

    申请日：2003-12-31

    申请人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    发明人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814

    摘要： An analog delay locked loop device includes a first block for receiving an internal clock signal and a reference clock signal to generate normal multi phase clock signal pairs and dummy multi phase clock signal pairs; and a second block for receiving the reference clock signal to generate a delay locked internal clock signal having a corrected duty cycle based on the normal multi phase clock signal pairs and the dummy multi phase clock signal pairs.

    摘要翻译： 模拟延迟锁定环路装置包括用于接收内部时钟信号的第一块和参考时钟信号，以产生正常的多相时钟信号对和虚拟多相时钟信号对; 以及第二块，用于接收参考时钟信号以产生具有基于正常多相时钟信号对和伪多相时钟信号对的校正占空比的延迟锁定内部时钟信号。

    Semiconductor memory device with reduced data access time
    6.
    发明授权
    Semiconductor memory device with reduced data access time 有权
    具有减少数据存取时间的半导体存储器件

    公开(公告)号：US06937535B2

    公开(公告)日：2005-08-30

    申请号：US10696144

    申请日：2003-10-28

    申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

    发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

    IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/00

    CPC分类号： G11C7/18 ,  G11C11/4087 ,  G11C11/4097

    摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

    摘要翻译： 存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于 从原始单元块或另一个单元块输出下一个指令。

    Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data
    7.
    发明授权
    Semiconductor memory device capable of accessing data in continuous burst mode regardless of location of accessed data 有权
    能够以连续脉冲串模式访问数据而不管访问数据的位置如何的半导体存储器件

    公开(公告)号：US06930951B2

    公开(公告)日：2005-08-16

    申请号：US10744322

    申请日：2003-12-22

    申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    IPC分类号： G11C8/08 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12

    CPC分类号： G11C7/1018

    摘要： There is provided a semiconductor memory device and a method for driving the same, which is capable of accessing data in a continuous burst mode regardless of locations of accessed data. The semiconductor memory device includes: a first bank including a first word line corresponding to a first row address; and a second bank including a second word line corresponding to a second row address, wherein the second row address is consecutive to the first row address. The method for driving a semiconductor memory device includes the steps of: receiving a first row address corresponding to a command; activating a word line of a first bank corresponding to the first row address; activating a word line of a second bank corresponding to a second row address, in which the second row address is consecutive to the first row address; sequentially accessing the predetermined number of data among the N data in a plurality of unit cells corresponding to the word line of the first bank; and sequentially accessing the remaining data in a plurality of unit cells corresponding to a word line of the second bank.

    摘要翻译： 提供了一种半导体存储器件及其驱动方法，其能够以连续的突发模式访问数据，而不管访问数据的位置如何。 半导体存储器件包括：第一存储体，包括对应于第一行地址的第一字线; 以及包括对应于第二行地址的第二字线的第二存储体，其中所述第二行地址与所述第一行地址连续。 驱动半导体存储器件的方法包括以下步骤：接收与命令对应的第一行地址; 激活对应于第一行地址的第一存储体的字线; 激活对应于第二行地址的第二存储体的字线，其中第二行地址与第一行地址连续; 在对应于第一存储单元的字线的多个单位单元中，依次访问N个数据中的预定数量的数据; 并且依次访问与第二存储体的字线对应的多个单位单元中的剩余数据。

    Semiconductor memory device with optimum refresh cycle according to temperature variation
    9.
    发明授权
    Semiconductor memory device with optimum refresh cycle according to temperature variation 失效
    半导体存储器件根据温度变化具有最佳的刷新周期

    公开(公告)号：US08520450B2

    公开(公告)日：2013-08-27

    申请号：US13196779

    申请日：2011-08-02

    申请人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    发明人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    IPC分类号： G11C7/06

    CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C2211/4061

    摘要： Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.

    摘要翻译： 公开了一种用于在半导体器件中产生刷新信号的方法和用于在半导体存储器件中执行刷新操作的方法。 一种产生刷新信号的方法包括测量半导体存储器件的温度，基于测量的温度产生温度控制电压，基于温度控制电压产生N位数字信号，并产生频率为 由N位数字信号决定。 产生温度控制电压包括产生在测量温度降低时增加的第一电流，并且随着测量温度的升高而降低，并产生温度控制电压。

    Semiconductor memory device with reduced data access time
    10.
    再颁专利
    Semiconductor memory device with reduced data access time 有权
    具有减少数据存取时间的半导体存储器件

    公开(公告)号：USRE42976E1

    公开(公告)日：2011-11-29

    申请号：US11897516

    申请日：2007-08-29

    申请人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

    发明人： Jin-Hong Ahn ,  Sang-Hoon Hong ,  Se-Jun Kim ,  Jae-Bum Ko

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/18 ,  G11C11/4087 ,  G11C11/4097

    摘要： A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a control block, one global bit line connection unit being allocated between the two cell blocks; and said control block for controlling output of data stored in each cell block to the global bit line and restoration of the outputted data of the global bit line to the original cell block or another cell block which is determined by depending upon whether data in response to a next instruction is outputted from the original cell block or another cell block.

    摘要翻译： 存储器件包括连接到全局位线的至少两个单元块，用于响应于指令输出数据; 至少一个全局位线连接单元，用于在控制块的控制下选择性地将全局位线连接到每个单元块，一个全局位线连接单元被分配在两个单元块之间; 以及所述控制块，用于控制存储在每个单元块中的数据到全局位线的输出，并将全局位线的输出数据恢复到原始单元块或另一个单元块，该单元块根据是否响应于 从原始单元块或另一个单元块输出下一个指令。