公开(公告)号：US20130163352A1

公开(公告)日：2013-06-27

申请号：US13445155

申请日：2012-04-12

申请人： Chang-Ho DO

发明人： Chang-Ho DO

IPC分类号： G11C7/10

CPC分类号： G11C29/785

摘要： A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device.

摘要翻译： 一种半导体存储器件包括多个维修熔丝单元，其被配置为分别对维修目标存储单元编制维修目标地址，其中至少一个维修保险丝单元用与维修目标地址不同的目的使用的数据信息进行编程，多个 每个地址比较单元被配置为将访问目标地址与修复目标地址的对应地址进行比较，并且确定是否执行修复操作;以及数据传送单元，被配置为将数据信息传送到半导体的相应电路 存储设备。

公开(公告)号：US08330531B2

公开(公告)日：2012-12-11

申请号：US13409379

申请日：2012-03-01

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4085 ,  G11C2211/4068

摘要： An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval.

摘要翻译： 内部负电压产生装置包括：第一内部负电压产生模块，被配置为产生低于接地电压的第一内部负电压; 第二内部负电压产生块，被配置为根据所述第一内部负电压产生第二内部负电压，所述第二内部负电压高于所述第一内部负电压并且低于所述接地电压; 以及初始驱动块，被配置为在活动操作时间间隔的初始设置时间间隔期间附加地将第二内部负电压端子驱动到所述第一内部负电压。

公开(公告)号：US08225150B2

公开(公告)日：2012-07-17

申请号：US13149683

申请日：2011-05-31

申请人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

发明人： Hwang Hur ,  Chang-Ho Do ,  Jae-Bum Ko ,  Jin-Il Chung

IPC分类号： G11C29/00 ,  G01R31/28 ,  H03M13/00

CPC分类号： G11C29/12 ,  G11C11/401

摘要： Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level.

摘要翻译： 半导体存储器件包括：包括多个单元的单元阵列; 以及测试电路，被配置为执行内置自应力（BISS）测试，以通过在运行的测试过程期间通过使用多个模式访问单元单元执行包括写入操作的多个内部操作来检测缺陷 在晶圆级别。

公开(公告)号：US08169837B2

公开(公告)日：2012-05-01

申请号：US12345636

申请日：2008-12-29

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C7/22

摘要： A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal.

摘要翻译： 半导体存储器件的位线均衡信号发生器在使能位线均衡信号的时段期间分阶段使用电源电压和泵浦电压，从而在最小化功耗的同时提高均衡速度和有效速度。 半导体存储器件包括位线均衡信号产生单元，其被配置为在位线均衡信号使能的周期的开始期间的第一激活周期期间驱动具有电源电压的输出端子，并且驱动输出端子 在第一激活周期之后的第二激活期间，高于电源电压的泵浦电压，从而输出位线均衡信号，以及位线均衡单元，其被配置为响应于位线均衡信号来均衡位线对。

公开(公告)号：US08054702B2

公开(公告)日：2011-11-08

申请号：US12472252

申请日：2009-05-26

申请人： Hwang Hur ,  Chang-Ho Do

发明人： Hwang Hur ,  Chang-Ho Do

IPC分类号： G11C7/00

CPC分类号： G11C29/34 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/16 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C2207/108

摘要： A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.

摘要翻译： 信号对准电路包括多个焊盘，1比特1比特并行地接收输入信号; 第一传送单元，用于将输入信号作为与内部时钟的第一时钟信号同步的第一信号传送，并且将输入信号作为与内部时钟的第二时钟信号同步的第二信号传送; 第二传送单元，用于与所述内部时钟的第二时钟信号同步地传送所述第一信号; 以及对准单元，用于对准从第一和第二传送单元传送的第一和第二信号，并输出对准的信号作为输出信号。

公开(公告)号：US08054113B2

公开(公告)日：2011-11-08

申请号：US12904763

申请日：2010-10-14

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal.

摘要翻译： 上电信号发生电路通过对与上电信号相对应的电源电压的目标电压电平提供预定的滞后特性来以预定的目标电压电平来转换上电信号。 上电信号发生电路包括：第一电压检测单元，其检测电源电压的第一目标电压电平以输出检测信号。 电路还包括第二电压检测单元，其响应于上电信号检测电源电压的第二目标电压电平，以输出控制信号，其中第二目标电压电平低于第一目标电压电平。 电路的上电信号驱动单元响应于检测信号而激活上电信号，并根据控制信号驱动上电信号。

公开(公告)号：US08040177B2

公开(公告)日：2011-10-18

申请号：US12815075

申请日：2010-06-14

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G05F1/10

CPC分类号： G05F1/465

摘要： An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

摘要翻译： 半导体器件的内部电压产生电路包括：第一电压驱动器，其被配置为在内部电压端子的电平低于目标电平的期间内上拉内部电压端子;以及第二电压驱动器， 在每个周期内的预定时间内对应于外部时钟的频率的内部电压端子。

公开(公告)号：US20110249517A1

公开(公告)日：2011-10-13

申请号：US13165697

申请日：2011-06-21

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C5/14

CPC分类号： G11C8/08

摘要： Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver.

摘要翻译： 半导体存储器件的字线驱动电路包括被配置为产生用于访问数据的阈值偏置电压的偏置发生器，被配置为在数据访问操作的初始阶段增加阈值偏置电压的过驱动器和被配置为激活 字线响应阈值偏置电压和从过驱动器输出的信号。

公开(公告)号：US07983097B2

公开(公告)日：2011-07-19

申请号：US12157236

申请日：2008-06-09

申请人： Jae-II Kim ,  Chang-Ho Do

发明人： Jae-II Kim ,  Chang-Ho Do

IPC分类号： G11C5/14

CPC分类号： G11C8/08

摘要： Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver.

摘要翻译： 半导体存储器件的字线驱动电路包括被配置为产生用于访问数据的阈值偏置电压的偏置发生器，被配置为在数据访问操作的初始阶段增加阈值偏置电压的过驱动器和被配置为激活 字线响应阈值偏置电压和从过驱动器输出的信号。

公开(公告)号：US07974142B2

公开(公告)日：2011-07-05

申请号：US12068583

申请日：2008-02-08

申请人： Chang-Ho Do ,  Jae-Il Kim

发明人： Chang-Ho Do ,  Jae-Il Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069

摘要： A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.

摘要翻译： 半导体存储器件包括：数据传送器，被配置为传送数据; 主驱动器，被配置为响应于控制信号将数据应用于数据传送器; 以及预驱动器，被配置为当数据传送器的电压电平高于逻辑阈值电压时降低数据传送器的电压电平，并且当数据传送器的电压电平为 低于启动控制信号之前的逻辑阈值电压。