公开(公告)号：US20110249517A1

公开(公告)日：2011-10-13

申请号：US13165697

申请日：2011-06-21

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C5/14

CPC分类号： G11C8/08

摘要： Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver.

摘要翻译： 半导体存储器件的字线驱动电路包括被配置为产生用于访问数据的阈值偏置电压的偏置发生器，被配置为在数据访问操作的初始阶段增加阈值偏置电压的过驱动器和被配置为激活 字线响应阈值偏置电压和从过驱动器输出的信号。

公开(公告)号：US07974142B2

公开(公告)日：2011-07-05

申请号：US12068583

申请日：2008-02-08

申请人： Chang-Ho Do ,  Jae-Il Kim

发明人： Chang-Ho Do ,  Jae-Il Kim

IPC分类号： G11C7/10

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069

摘要： A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.

摘要翻译： 半导体存储器件包括：数据传送器，被配置为传送数据; 主驱动器，被配置为响应于控制信号将数据应用于数据传送器; 以及预驱动器，被配置为当数据传送器的电压电平高于逻辑阈值电压时降低数据传送器的电压电平，并且当数据传送器的电压电平为 低于启动控制信号之前的逻辑阈值电压。

公开(公告)号：US07839709B2

公开(公告)日：2010-11-23

申请号：US12005919

申请日：2007-12-28

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C29/12 ,  G11C29/1201

摘要： A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality of global lines, in response to an output control signal activated after a delay time corresponding to an additive latency from entry of a read operation in a test mode. The data output unit aligns data outputted from the output data select unit and outputs the aligned data through data pads.

摘要翻译： 半导体存储器件能够在实际操作的相同条件下减少测试时间。 半导体存储器件包括输出数据选择单元和数据输出单元。 输出数据选择单元响应于在对应于在测试模式中的读取操作的输入的附加等待时间的延迟时间之后激活的输出控制信号，选择性地输出加载在多条全局线路上的有效数据。 数据输出单元对准从输出数据选择单元输出的数据，并通过数据垫输出对准的数据。

公开(公告)号：US07636272B2

公开(公告)日：2009-12-22

申请号：US12288879

申请日：2008-10-24

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C7/1075 ,  G11C7/1027 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/16 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

摘要： A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

公开(公告)号：US20090059689A1

公开(公告)日：2009-03-05

申请号：US12068583

申请日：2008-02-08

申请人： Chang-Ho Do ,  Jae-Il Kim

发明人： Chang-Ho Do ,  Jae-Il Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069

摘要： A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.

摘要翻译： 半导体存储器件包括：数据传送器，被配置为传送数据; 主驱动器，被配置为响应于控制信号将数据应用于数据传送器; 以及预驱动器，被配置为当数据传送器的电压电平高于逻辑阈值电压时降低数据传送器的电压电平，并且当数据传送器的电压电平为 低于启动控制信号之前的逻辑门限电压。

公开(公告)号：US07447095B2

公开(公告)日：2008-11-04

申请号：US11529202

申请日：2006-09-27

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1075 ,  G11C7/1027 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/16 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

摘要： A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

摘要翻译： 具有执行与外部设备的串行输入/输出（I / O）通信的多个端口的多端口存储器件以及通过多个全局I / O与端口执行并行I / O通信的多个存储体 线条。 多端口存储装置包括：写时钟生成单元，用于仅在应用写数据时选择性地切换写时钟; 写入控制单元，用于响应写入时钟和写入命令产生写入标志信号组和写入驱动器使能信号; 数据锁存单元，用于通过在写入标志信号组的控制下存储脉冲串写入数据来输出中间写入数据; 以及写入驱动器，用于接收中间写入数据，以响应于写入驱动器使能信号和数据掩码信号组而将最终写入数据写入对应存储体的存储单元。

公开(公告)号：US20070073982A1

公开(公告)日：2007-03-29

申请号：US11529202

申请日：2006-09-27

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G11C7/1027 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/16 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

摘要： A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

摘要翻译： 具有执行与外部设备的串行输入/输出（I / O）通信的多个端口的多端口存储器件以及通过多个全局I / O与端口执行并行I / O通信的多个存储体 线条。 多端口存储装置包括：写时钟生成单元，用于仅在应用写数据时选择性地切换写时钟; 写入控制单元，用于响应写入时钟和写入命令产生写入标志信号组和写入驱动器使能信号; 数据锁存单元，用于通过在写入标志信号组的控制下存储脉冲串写入数据来输出中间写入数据; 以及写入驱动器，用于接收中间写入数据，以响应于写入驱动器使能信号和数据掩码信号组而将最终写入数据写入对应存储体的存储单元。

公开(公告)号：US20070069804A1

公开(公告)日：2007-03-29

申请号：US11528282

申请日：2006-09-28

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G05F1/10

CPC分类号： G11C11/4085 ,  G11C5/145 ,  G11C8/08 ,  G11C11/4074

摘要： A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

摘要翻译： 高电压发生器包括：用于将参考电压与高电压进行比较并检测高电压电平的检测单元; 振荡器选择单元，用于响应于检测单元的输出信号和对应于数据操作模式的选择信号产生第一控制信号和第二控制信号; 用于响应于所述第一控制信号和所述第二控制信号产生具有不同频率的时钟信号的振荡器; 以及用于通过响应于时钟信号执行电荷泵送操作来产生高电压的泵送单元。

公开(公告)号：US08139437B2

公开(公告)日：2012-03-20

申请号：US13165697

申请日：2011-06-21

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver.

摘要翻译： 半导体存储器件的字线驱动电路包括被配置为产生用于访问数据的阈值偏置电压的偏置发生器，被配置为在数据访问操作的初始阶段增加阈值偏置电压的过驱动器和被配置为激活 字线响应阈值偏置电压和从过驱动器输出的信号。

公开(公告)号：US08031552B2

公开(公告)日：2011-10-04

申请号：US12717011

申请日：2010-03-03

申请人： Jin-Il Chung ,  Jae-Il Kim ,  Chang-Ho Do ,  Hwang Hur

发明人： Jin-Il Chung ,  Jae-Il Kim ,  Chang-Ho Do ,  Hwang Hur

IPC分类号： G11C8/00

CPC分类号： G11C7/1075 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C29/26 ,  G11C29/32

摘要： A multi-port memory device includes ports, banks, a global data bus, an input/output (I/O) controller, mode register set (MRS), a clock generator, and a test I/O controller. The I/O controller transmits a test signal to the global data bus in response to a mode register enable signal. The MRS generates a test enable signal in response to the mode register enable signal and outputs a mode selection signal which determines a data transmission mode of a test I/O signal in response to the test signal. The clock generator receives an external clock and generates an internal clock based on the external clock in response to the mode selection signal. The test I/O controller inputs/outputs the test I/O signal in synchronism with the internal clock. The mode register enable signal active during a test operation mode for testing a core area of the banks.

摘要翻译： 多端口存储器件包括端口，存储体，全局数据总线，输入/输出（I / O）控制器，模式寄存器集（MRS），时钟发生器和测试I / O控制器。 I / O控制器响应于模式寄存器使能信号将测试信号发送到全局数据总线。 MRS响应于模式寄存器使能信号产生测试使能信号，并输出一个模式选择信号，该模式选择信号响应于测试信号确定测试I / O信号的数据传输模式。 时钟发生器响应于模式选择信号接收外部时钟并基于外部时钟生成内部时钟。 测试I / O控制器与内部时钟同步输入/输出测试I / O信号。 在测试操作模式期间模式寄存器使能信号有效，用于测试存储体的核心区域。