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    Asynchronous instruction execution apparatus with execution modules invoking external calculation resources
    1.
    发明授权
    Asynchronous instruction execution apparatus with execution modules invoking external calculation resources 有权

    公开(公告)号：US10338921B2

    公开(公告)日：2019-07-02

    申请号：US15482550

    申请日：2017-04-07

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Shaola Yang ,  Xiaocheng Liu ,  Zhen Xu

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F15/80

    Abstract: An asynchronous instruction execution apparatus and method are provided. The asynchronous instruction execution apparatus includes a vector execution unit control VXUC module and n vector execution unit data VXUD modules, where n is a positive integer. The VXUC module is configured to perform instruction decoding and token management. The n VXUD modules are cascaded, separately connected to the VXUC module, and configured to invoke an external calculation resource to perform data calculation. A bit width of data processed by the asynchronous instruction execution apparatus is M, a bit width of each VXUD module is N, and n=M/N. The asynchronous instruction execution apparatus is divided into two parts: the VXUC and the VXUD.

    Test apparatus and testable asynchronous circuit
    2.
    发明授权
    Test apparatus and testable asynchronous circuit 有权

    公开(公告)号：US10209299B2

    公开(公告)日：2019-02-19

    申请号：US15432741

    申请日：2017-02-14

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen Xu ,  Yuqing Zhao ,  Xiaocheng Liu

    IPC: G01R31/28 ,  G06F11/00 ,  G01R31/317 ,  G06F11/25 ,  G01R31/3185

    Abstract: Disclosed are a test apparatus and a testable asynchronous circuit. The test apparatus includes: a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first selector, a second selector, a D flip-flop, and a first output end. The first input end is configured to input a data signal or a test result of a previous circuit under test; the second input end is configured to input a test excitation signal or a test result that is output by a previous test apparatus; the third input end is configured to input a clock signal; the fourth input end is configured to input a selection signal; and the fifth input end is configured to input a selection signal.

    Graphene fiber and prepartion method thereof
    4.
    发明授权
    Graphene fiber and prepartion method thereof 有权

    公开(公告)号：US10145029B2

    公开(公告)日：2018-12-04

    申请号：US14559630

    申请日：2014-12-03

    Applicant: Huawei Technologies Co., Ltd. ,  Zhejiang University

    Inventor： Xiaosong Zhou ,  Yan Xu ,  Chao Gao ,  Zhen Xu

    IPC: D01F9/12 ,  D01D5/06 ,  D01F1/09 ,  D01F11/10 ,  C01B32/182 ,  C01B32/194

    Abstract: A graphene fiber and a preparation method thereof, where the graphene fiber is a composite fiber of metal nanowire doped graphene fiber, and principal components of the composite fiber are graphene and metal nanowires, a mass ratio of metal nanowires is 0.1%-50%, the graphene is in a form of sheet, and both the metal nanowires and graphene sheets are arranged in parallel along an axial direction of the graphene fiber. The metal nanowire doped graphene fiber is a new type of a high performance multi-functional fiber material, which achieves a significant improvement in electrical conductivity of graphene fibers through doping of metal nanowires and meanwhile demonstrates excellent tensile strength and toughness. The metal nanowire doped graphene fiber has great potential application value in a plurality of fields, for example, it is used as a lightweight flexible wire.

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