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1.发明申请Signal Calibration Method and Client Circuit and Transmission System Using the Same 审中-公开信号校准方法及使用其的客户端电路和传输系统公开(公告)号：US20120288046A1
公开(公告)日：2012-11-15
申请号：US13469081
申请日：2012-05-10
Applicant: Hsueh-Yi Lee , Chih-Wei Tang , Kuan-Hua Chen , Wing-Kai Tang
Inventor： Hsueh-Yi Lee , Chih-Wei Tang , Kuan-Hua Chen , Wing-Kai Tang
IPC: H04L7/04
CPC classification number: H04L7/0037 , H04L7/0008 , H04L7/0041 , H04L7/046 , H04L25/14
Abstract: A signal calibration method for synchronizing a clock signal and at least one data signal in a transmission system is disclosed. The signal calibration method comprises detecting at least one transmission time difference between the clock signal and the at least one data signal transmitted in the transmission system, calculating a plurality of delay periods of the clock signal and the at least one data signal according to the at least one transmission time difference, and respectively delaying the clock signal and the at least one data signal for the plurality of delay periods to synchronize the clock signal and the at least one data signal.
Abstract translation: 公开了一种在传输系统中同步时钟信号和至少一个数据信号的信号校准方法。 所述信号校准方法包括：检测所述时钟信号与所述传输系统中传输的所述至少一个数据信号之间的至少一个传输时间差，根据所述时钟信号和所述至少一个数据信号计算所述时钟信号和所述至少一个数据信号的多个延迟周期 至少一个传输时间差，并且分别延迟所述多个延迟周期的时钟信号和所述至少一个数据信号，以使所述时钟信号和所述至少一个数据信号同步。
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公开(公告)号：US08228276B2
公开(公告)日：2012-07-24
申请号：US11533374
申请日：2006-09-20
Applicant: Hsueh-Yi Lee , Chih-Wei Tang , Wing-Kai Tang
Inventor： Hsueh-Yi Lee , Chih-Wei Tang , Wing-Kai Tang
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G3/3655 , G09G2310/0297 , G09G2320/0209 , G09G2320/0247
Abstract: A display driver apparatus and an inversion method thereof are provided. The display driver apparatus includes a gate drive unit, a source drive unit, a multiplexer unit and a common voltage generation unit. The gate drive unit is used to generate a gate signal for turning on/off sub-pixels. The source drive unit is used to generate a source signal required by the display panel. The multiplexer unit is used to regulate the sequence for the source signal to be delivered to the sub-pixels. The common voltage generation unit is used to generate a common voltage and switch the level of the common voltage during the enable period of the gate signal.
Abstract translation: 提供了一种显示驱动装置及其反演方法。 显示驱动器装置包括栅极驱动单元，源极驱动单元，多路复用器单元和公共电压产生单元。 栅极驱动单元用于产生用于打开/关闭子像素的栅极信号。 源驱动单元用于产生显示面板所需的源信号。 多路复用器单元用于调节要传送到子像素的源信号的序列。 公共电压产生单元用于产生公共电压并在门信号的使能期间切换公共电压的电平。
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公开(公告)号：US20070296675A1
公开(公告)日：2007-12-27
申请号：US11533374
申请日：2006-09-20
Applicant: Hsueh-Yi Lee , Chih-Wei Tang , Wing-Kai Tang
Inventor： Hsueh-Yi Lee , Chih-Wei Tang , Wing-Kai Tang
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G3/3655 , G09G2310/0297 , G09G2320/0209 , G09G2320/0247
Abstract: A display driver apparatus and an inversion method thereof are provided. The display driver apparatus includes a gate drive unit, a source drive unit, a multiplexer unit and a common voltage generation unit. The gate drive unit is used to generate a gate signal for turning on/off sub-pixels. The source drive unit is used to generate a source signal required by the display panel. The multiplexer unit is used to regulate the sequence for the source signal to be delivered to the sub-pixels. The common voltage generation unit is used to generate a common voltage and switch the level of the common voltage during the enable period of the gate signal.
Abstract translation: 提供了一种显示驱动装置及其反演方法。 显示驱动器装置包括栅极驱动单元，源极驱动单元，多路复用器单元和公共电压产生单元。 栅极驱动单元用于产生用于打开/关闭子像素的栅极信号。 源驱动单元用于产生显示面板所需的源信号。 多路复用器单元用于调节要传送到子像素的源信号的序列。 公共电压产生单元用于产生公共电压并在门信号的使能期间切换公共电压的电平。
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公开(公告)号：US20110169801A1
公开(公告)日：2011-07-14
申请号：US12889436
申请日：2010-09-24
Applicant: Jin-Sheng Hsieh , Hsueh-Yi Lee , Wing-Kai Tang
Inventor： Jin-Sheng Hsieh , Hsueh-Yi Lee , Wing-Kai Tang
IPC: G09G5/00
CPC classification number: G09G3/3659 , G09G3/2011 , G09G5/003 , G09G5/10 , G09G2310/0248
Abstract: A driving apparatus of a display is disclosed. The driving apparatus mentioned above includes a digital-to-analog converter circuit and an output buffer circuit. The digital-to-analog converting circuit receives a display data with a digital format for generating a gray-level voltage. The output buffer circuit has an output terminal to output an output signal. The output buffer circuit receives the gray-level voltage, a pre-charge enable signal and the output signal and provides a pre-charge output signal to the output terminal of the output buffering circuit according to the pre-charge enable signal and a comparison result of the gray-level voltage and the output signal.
Abstract translation: 公开了一种显示器的驱动装置。 上述驱动装置包括数模转换器电路和输出缓冲电路。 数模转换电路接收具有用于产生灰度电压的数字格式的显示数据。 输出缓冲电路具有用于输出输出信号的输出端子。 输出缓冲电路接收灰度电压，预充电使能信号和输出信号，并根据预充电使能信号向输出缓冲电路的输出端提供预充电输出信号，并将比较结果 的灰度电压和输出信号。
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Patent Agency Ranking
公开(公告)号：US08599185B2
公开(公告)日：2013-12-03
申请号：US12889436
申请日：2010-09-24
Applicant: Jin-Sheng Hsieh , Hsueh-Yi Lee , Wing-Kai Tang
Inventor： Jin-Sheng Hsieh , Hsueh-Yi Lee , Wing-Kai Tang
IPC: G09G5/00
CPC classification number: G09G3/3659 , G09G3/2011 , G09G5/003 , G09G5/10 , G09G2310/0248
Abstract: A driving apparatus of a display is disclosed. The driving apparatus mentioned above includes a digital-to-analog converter circuit and an output buffer circuit. The digital-to-analog converting circuit receives a display data with a digital format for generating a gray-level voltage. The output buffer circuit has an output terminal to output an output signal. The output buffer circuit receives the gray-level voltage, a pre-charge enable signal and the output signal and provides a pre-charge output signal to the output terminal of the output buffering circuit according to the pre-charge enable signal and a comparison result of the gray-level voltage and the output signal.
Abstract translation: 公开了一种显示器的驱动装置。 上述驱动装置包括数模转换器电路和输出缓冲电路。 数模转换电路接收具有用于产生灰度电压的数字格式的显示数据。 输出缓冲电路具有用于输出输出信号的输出端子。 输出缓冲电路接收灰度电压，预充电使能信号和输出信号，并根据预充电使能信号向输出缓冲电路的输出端提供预充电输出信号，并将比较结果 的灰度电压和输出信号。
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6.发明授权Method of calibrating signal skews in MIPI and related transmission system 有权在MIPI和相关传输系统中校准信号偏移的方法公开(公告)号：US08886988B2
公开(公告)日：2014-11-11
申请号：US13231972
申请日：2011-09-14
Applicant: Ching-Chun Lin , Chih-Wei Tang , Hsueh-Yi Lee , Yu-Hsun Peng
Inventor： Ching-Chun Lin , Chih-Wei Tang , Hsueh-Yi Lee , Yu-Hsun Peng
CPC classification number: H04L7/0041 , G06F1/10 , H04L7/0037 , H04L7/033
Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.
Abstract translation: 在校准模式下，时钟信号和数据信号分别经由MIPI的时钟通道和数据通道发送。 通过调整时钟信号的相位来提供测试时钟信号，并且通过调整数据信号的相位来提供测试数据信号。 通过根据测试时钟信号锁存测试数据信号，可以获取锁存的数据，以确定对应于时钟通道和数据通道的优化的相位关系。 当在正常模式下发送时钟信号和数据信号时，可以根据优化的相位关系调整时钟通道和数据通道的信号延迟。
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7.发明申请公开(公告)号：US20120294401A1
公开(公告)日：2012-11-22
申请号：US13231972
申请日：2011-09-14
Applicant: Ching-Chun Lin , Chih-Wei Tang , Hsueh-Yi Lee , Yu-Hsun Peng
Inventor： Ching-Chun Lin , Chih-Wei Tang , Hsueh-Yi Lee , Yu-Hsun Peng
IPC: H04L7/04
CPC classification number: H04L7/0041 , G06F1/10 , H04L7/0037 , H04L7/033
Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.
Abstract translation: 在校准模式下，时钟信号和数据信号分别经由MIPI的时钟通道和数据通道发送。 通过调整时钟信号的相位来提供测试时钟信号，并且通过调整数据信号的相位来提供测试数据信号。 通过根据测试时钟信号锁存测试数据信号，可以获取锁存的数据，以确定对应于时钟通道和数据通道的优化的相位关系。 当在正常模式下发送时钟信号和数据信号时，可以根据优化的相位关系调整时钟通道和数据通道的信号延迟。
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公开(公告)号：US20070159887A1
公开(公告)日：2007-07-12
申请号：US11532054
申请日：2006-09-14
Applicant: Yi Te Shih , Jer Hao Hsu , Yi-Ti Wang , Hsueh-Yi Lee
Inventor： Yi Te Shih , Jer Hao Hsu , Yi-Ti Wang , Hsueh-Yi Lee
CPC classification number: G11C16/0491 , G11C16/12 , G11C16/3427 , G11C16/3459
Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.
Abstract translation: 示出了解决编程干扰效应的实施例。 具有编程电压和接地之间的幅度的中等电压被施加到受到编程干扰效应的单元中的金属位线。
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公开(公告)号：US07593264B2
公开(公告)日：2009-09-22
申请号：US11532054
申请日：2006-09-14
Applicant: Yi Te Shih , Jer-Hao Hsu , Yi-Ti Wang , Hsueh-Yi Lee
Inventor： Yi Te Shih , Jer-Hao Hsu , Yi-Ti Wang , Hsueh-Yi Lee
IPC: G11C16/04
CPC classification number: G11C16/0491 , G11C16/12 , G11C16/3427 , G11C16/3459
Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.
Abstract translation: 示出了解决编程干扰效应的实施例。 具有编程电压和接地之间的幅度的中等电压被施加到受到编程干扰效应的单元中的金属位线。
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